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Loading design for application trce from file prox_detect_impl1.ncd.
Design name: prox_detect
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-4000HC
Package:     CSBGA132
Performance: 5
Loading device for application trce from file 'xo2c4000.nph' in environment: C:/Program Files/diamond/3.14/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 36.4.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.14.0.75.2
Fri Mar 07 11:30:28 2025

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2024 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o prox_detect_impl1.twr -gui -msgset C:/Users/lumfl/Downloads/NetDisk/V4.0/STEP-MXO2/myTrafficLight/promote.xml prox_detect_impl1.ncd prox_detect_impl1.prf 
Design file:     prox_detect_impl1.ncd
Preference file: prox_detect_impl1.prf
Device,speed:    LCMXO2-4000HC,5
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

Report Type:     based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "clk_c" 41.487000 MHz ;
            4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 10.303ns (weighted slack = -2699.386ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat2[10]  (from dat_valid +)
   Destination:    FF         Data in        buzz_ctrl  (to clk_c +)

   Delay:               2.105ns  (40.9% logic, 59.1% route), 2 logic levels.

 Constraint Details:

      2.105ns physical path delay u2/SLICE_1165 to SLICE_534 exceeds
      0.092ns delay constraint less
      8.140ns skew and
      0.150ns DIN_SET requirement (totaling -8.198ns) by 10.303ns

 Physical Path Details:

      Data path u2/SLICE_1165 to SLICE_534:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C17A.CLK to      R8C17A.Q0 u2/SLICE_1165 (from dat_valid)
ROUTE         8     1.244      R8C17A.Q0 to      R7C17A.A0 dist[1]
CTOF_DEL    ---     0.452      R7C17A.A0 to      R7C17A.F0 SLICE_534
ROUTE         1     0.000      R7C17A.F0 to     R7C17A.DI0 buzz_ctrl4 (to clk_c)
                  --------
                    2.105   (40.9% logic, 59.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.409     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     4.662      R2C16A.Q0 to     R8C17A.CLK dat_valid
                  --------
                   12.302   (17.8% logic, 82.2% route), 3 logic levels.

      Destination Clock Path clk to SLICE_534:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R7C17A.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 9.780ns (weighted slack = -2562.360ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat2[11]  (from dat_valid +)
   Destination:    FF         Data in        buzz_ctrl  (to clk_c +)

   Delay:               1.582ns  (54.4% logic, 45.6% route), 2 logic levels.

 Constraint Details:

      1.582ns physical path delay u2/SLICE_1165 to SLICE_534 exceeds
      0.092ns delay constraint less
      8.140ns skew and
      0.150ns DIN_SET requirement (totaling -8.198ns) by 9.780ns

 Physical Path Details:

      Data path u2/SLICE_1165 to SLICE_534:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C17A.CLK to      R8C17A.Q1 u2/SLICE_1165 (from dat_valid)
ROUTE         8     0.721      R8C17A.Q1 to      R7C17A.C0 dist[2]
CTOF_DEL    ---     0.452      R7C17A.C0 to      R7C17A.F0 SLICE_534
ROUTE         1     0.000      R7C17A.F0 to     R7C17A.DI0 buzz_ctrl4 (to clk_c)
                  --------
                    1.582   (54.4% logic, 45.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.409     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     4.662      R2C16A.Q0 to     R8C17A.CLK dat_valid
                  --------
                   12.302   (17.8% logic, 82.2% route), 3 logic levels.

      Destination Clock Path clk to SLICE_534:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R7C17A.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 90.110ns (weighted slack = -2279.131ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        led_reg  (to clk_c +)

   Delay:              87.844ns  (27.4% logic, 72.6% route), 55 logic levels.

 Constraint Details:

     87.844ns physical path delay u1/SLICE_1346 to SLICE_573 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 24.104ns)
      0.953ns delay constraint less
      3.069ns skew and
      0.150ns DIN_SET requirement (totaling -2.266ns) by 90.110ns

 Physical Path Details:

      Data path u1/SLICE_1346 to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19C.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19C.B0 to      R5C19C.F0 u2/u1/SLICE_1155
ROUTE         4     0.892      R5C19C.F0 to      R7C19A.A1 u2/u1/shift_reg_61[34]
CTOF_DEL    ---     0.452      R7C19A.A1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     0.919     R10C27B.F1 to     R10C26B.B1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452     R10C26B.B1 to     R10C26B.F1 SLICE_915
ROUTE         2     1.188     R10C26B.F1 to      R9C25D.B1 u2.u1._l31.shift_reg_480_c3
CTOF_DEL    ---     0.452      R9C25D.B1 to      R9C25D.F1 SLICE_931
ROUTE        11     1.216      R9C25D.F1 to      R8C23D.B0 lux_data[16]
CTOF_DEL    ---     0.452      R8C23D.B0 to      R8C23D.F0 SLICE_573
ROUTE         1     0.000      R8C23D.F0 to     R8C23D.DI0 led_reg6_i (to clk_c)
                  --------
                   87.844   (27.4% logic, 72.6% route), 55 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R8C23D.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 90.078ns (weighted slack = -2278.321ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        led_reg  (to clk_c +)

   Delay:              87.812ns  (26.9% logic, 73.1% route), 54 logic levels.

 Constraint Details:

     87.812ns physical path delay u1/SLICE_1346 to SLICE_573 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 24.104ns)
      0.953ns delay constraint less
      3.069ns skew and
      0.150ns DIN_SET requirement (totaling -2.266ns) by 90.078ns

 Physical Path Details:

      Data path u1/SLICE_1346 to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.697      R5C19A.F0 to      R7C19A.C1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19A.C1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     0.919     R10C27B.F1 to     R10C26B.B1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452     R10C26B.B1 to     R10C26B.F1 SLICE_915
ROUTE         2     1.188     R10C26B.F1 to      R9C25D.B1 u2.u1._l31.shift_reg_480_c3
CTOF_DEL    ---     0.452      R9C25D.B1 to      R9C25D.F1 SLICE_931
ROUTE        11     1.216      R9C25D.F1 to      R8C23D.B0 lux_data[16]
CTOF_DEL    ---     0.452      R8C23D.B0 to      R8C23D.F0 SLICE_573
ROUTE         1     0.000      R8C23D.F0 to     R8C23D.DI0 led_reg6_i (to clk_c)
                  --------
                   87.812   (26.9% logic, 73.1% route), 54 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R8C23D.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 89.915ns (weighted slack = -2274.198ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        led_reg  (to clk_c +)

   Delay:              87.649ns  (27.5% logic, 72.5% route), 55 logic levels.

 Constraint Details:

     87.649ns physical path delay u1/SLICE_1346 to SLICE_573 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 24.104ns)
      0.953ns delay constraint less
      3.069ns skew and
      0.150ns DIN_SET requirement (totaling -2.266ns) by 89.915ns

 Physical Path Details:

      Data path u1/SLICE_1346 to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19A.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19A.B0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.697      R5C19A.F0 to      R7C19A.C1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19A.C1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     0.919     R10C27B.F1 to     R10C26B.B1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452     R10C26B.B1 to     R10C26B.F1 SLICE_915
ROUTE         2     1.188     R10C26B.F1 to      R9C25D.B1 u2.u1._l31.shift_reg_480_c3
CTOF_DEL    ---     0.452      R9C25D.B1 to      R9C25D.F1 SLICE_931
ROUTE        11     1.216      R9C25D.F1 to      R8C23D.B0 lux_data[16]
CTOF_DEL    ---     0.452      R8C23D.B0 to      R8C23D.F0 SLICE_573
ROUTE         1     0.000      R8C23D.F0 to     R8C23D.DI0 led_reg6_i (to clk_c)
                  --------
                   87.649   (27.5% logic, 72.5% route), 55 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R8C23D.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 89.893ns (weighted slack = -2273.642ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        led_reg  (to clk_c +)

   Delay:              87.627ns  (27.5% logic, 72.5% route), 55 logic levels.

 Constraint Details:

     87.627ns physical path delay u1/SLICE_1346 to SLICE_573 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 24.104ns)
      0.953ns delay constraint less
      3.069ns skew and
      0.150ns DIN_SET requirement (totaling -2.266ns) by 89.893ns

 Physical Path Details:

      Data path u1/SLICE_1346 to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19C.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19C.B0 to      R5C19C.F0 u2/u1/SLICE_1155
ROUTE         4     0.892      R5C19C.F0 to      R7C19A.A1 u2/u1/shift_reg_61[34]
CTOF_DEL    ---     0.452      R7C19A.A1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.328     R13C25D.F1 to     R13C28A.D0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C28A.D0 to     R13C28A.F0 u2/u1/SLICE_1228
ROUTE         1     0.937     R13C28A.F0 to     R12C28C.A1 u2/u1/shift_reg_365_c1
CTOF_DEL    ---     0.452     R12C28C.A1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     0.919     R10C27B.F1 to     R10C26B.B1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452     R10C26B.B1 to     R10C26B.F1 SLICE_915
ROUTE         2     1.188     R10C26B.F1 to      R9C25D.B1 u2.u1._l31.shift_reg_480_c3
CTOF_DEL    ---     0.452      R9C25D.B1 to      R9C25D.F1 SLICE_931
ROUTE        11     1.216      R9C25D.F1 to      R8C23D.B0 lux_data[16]
CTOF_DEL    ---     0.452      R8C23D.B0 to      R8C23D.F0 SLICE_573
ROUTE         1     0.000      R8C23D.F0 to     R8C23D.DI0 led_reg6_i (to clk_c)
                  --------
                   87.627   (27.5% logic, 72.5% route), 55 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R8C23D.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 89.883ns (weighted slack = -2273.389ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        led_reg  (to clk_c +)

   Delay:              87.617ns  (26.5% logic, 73.5% route), 53 logic levels.

 Constraint Details:

     87.617ns physical path delay u1/SLICE_1346 to SLICE_573 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 24.104ns)
      0.953ns delay constraint less
      3.069ns skew and
      0.150ns DIN_SET requirement (totaling -2.266ns) by 89.883ns

 Physical Path Details:

      Data path u1/SLICE_1346 to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.923      R5C19A.F0 to      R7C19B.B1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19B.B1 to      R7C19B.F1 u2/u1/SLICE_1149
ROUTE         4     0.895      R7C19B.F1 to      R8C19D.A0 u2/u1/shift_reg_71[34]
CTOF_DEL    ---     0.452      R8C19D.A0 to      R8C19D.F0 u2/u1/SLICE_1142
ROUTE         6     1.788      R8C19D.F0 to     R10C18C.D0 u2/u1/shift_reg_84[33]
CTOF_DEL    ---     0.452     R10C18C.D0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     0.919     R10C27B.F1 to     R10C26B.B1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452     R10C26B.B1 to     R10C26B.F1 SLICE_915
ROUTE         2     1.188     R10C26B.F1 to      R9C25D.B1 u2.u1._l31.shift_reg_480_c3
CTOF_DEL    ---     0.452      R9C25D.B1 to      R9C25D.F1 SLICE_931
ROUTE        11     1.216      R9C25D.F1 to      R8C23D.B0 lux_data[16]
CTOF_DEL    ---     0.452      R8C23D.B0 to      R8C23D.F0 SLICE_573
ROUTE         1     0.000      R8C23D.F0 to     R8C23D.DI0 led_reg6_i (to clk_c)
                  --------
                   87.617   (26.5% logic, 73.5% route), 53 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R8C23D.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 89.861ns (weighted slack = -2272.833ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        led_reg  (to clk_c +)

   Delay:              87.595ns  (27.0% logic, 73.0% route), 54 logic levels.

 Constraint Details:

     87.595ns physical path delay u1/SLICE_1346 to SLICE_573 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 24.104ns)
      0.953ns delay constraint less
      3.069ns skew and
      0.150ns DIN_SET requirement (totaling -2.266ns) by 89.861ns

 Physical Path Details:

      Data path u1/SLICE_1346 to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.697      R5C19A.F0 to      R7C19A.C1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19A.C1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.328     R13C25D.F1 to     R13C28A.D0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C28A.D0 to     R13C28A.F0 u2/u1/SLICE_1228
ROUTE         1     0.937     R13C28A.F0 to     R12C28C.A1 u2/u1/shift_reg_365_c1
CTOF_DEL    ---     0.452     R12C28C.A1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     0.919     R10C27B.F1 to     R10C26B.B1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452     R10C26B.B1 to     R10C26B.F1 SLICE_915
ROUTE         2     1.188     R10C26B.F1 to      R9C25D.B1 u2.u1._l31.shift_reg_480_c3
CTOF_DEL    ---     0.452      R9C25D.B1 to      R9C25D.F1 SLICE_931
ROUTE        11     1.216      R9C25D.F1 to      R8C23D.B0 lux_data[16]
CTOF_DEL    ---     0.452      R8C23D.B0 to      R8C23D.F0 SLICE_573
ROUTE         1     0.000      R8C23D.F0 to     R8C23D.DI0 led_reg6_i (to clk_c)
                  --------
                   87.595   (27.0% logic, 73.0% route), 54 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R8C23D.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 89.834ns (weighted slack = -2272.150ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        led_reg  (to clk_c +)

   Delay:              87.568ns  (27.0% logic, 73.0% route), 54 logic levels.

 Constraint Details:

     87.568ns physical path delay u1/SLICE_1346 to SLICE_573 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 24.104ns)
      0.953ns delay constraint less
      3.069ns skew and
      0.150ns DIN_SET requirement (totaling -2.266ns) by 89.834ns

 Physical Path Details:

      Data path u1/SLICE_1346 to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.923      R5C19A.F0 to      R7C19B.B1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19B.B1 to      R7C19B.F1 u2/u1/SLICE_1149
ROUTE         4     0.399      R7C19B.F1 to      R7C19B.C0 u2/u1/shift_reg_71[34]
CTOF_DEL    ---     0.452      R7C19B.C0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     0.919     R10C27B.F1 to     R10C26B.B1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452     R10C26B.B1 to     R10C26B.F1 SLICE_915
ROUTE         2     1.188     R10C26B.F1 to      R9C25D.B1 u2.u1._l31.shift_reg_480_c3
CTOF_DEL    ---     0.452      R9C25D.B1 to      R9C25D.F1 SLICE_931
ROUTE        11     1.216      R9C25D.F1 to      R8C23D.B0 lux_data[16]
CTOF_DEL    ---     0.452      R8C23D.B0 to      R8C23D.F0 SLICE_573
ROUTE         1     0.000      R8C23D.F0 to     R8C23D.DI0 led_reg6_i (to clk_c)
                  --------
                   87.568   (27.0% logic, 73.0% route), 54 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R8C23D.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.


Error: The following path exceeds requirements by 89.831ns (weighted slack = -2272.074ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        led_reg  (to clk_c +)

   Delay:              87.565ns  (27.5% logic, 72.5% route), 55 logic levels.

 Constraint Details:

     87.565ns physical path delay u1/SLICE_1346 to SLICE_573 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 24.104ns)
      0.953ns delay constraint less
      3.069ns skew and
      0.150ns DIN_SET requirement (totaling -2.266ns) by 89.831ns

 Physical Path Details:

      Data path u1/SLICE_1346 to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19C.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19C.B0 to      R5C19C.F0 u2/u1/SLICE_1155
ROUTE         4     0.923      R5C19C.F0 to      R7C19D.B0 u2/u1/shift_reg_61[34]
CTOF_DEL    ---     0.452      R7C19D.B0 to      R7C19D.F0 u2/u1/SLICE_1151
ROUTE         4     0.559      R7C19D.F0 to      R7C19B.D0 u2/u1/shift_reg_71[33]
CTOF_DEL    ---     0.452      R7C19B.D0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     0.919     R10C27B.F1 to     R10C26B.B1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452     R10C26B.B1 to     R10C26B.F1 SLICE_915
ROUTE         2     1.188     R10C26B.F1 to      R9C25D.B1 u2.u1._l31.shift_reg_480_c3
CTOF_DEL    ---     0.452      R9C25D.B1 to      R9C25D.F1 SLICE_931
ROUTE        11     1.216      R9C25D.F1 to      R8C23D.B0 lux_data[16]
CTOF_DEL    ---     0.452      R8C23D.B0 to      R8C23D.F0 SLICE_573
ROUTE         1     0.000      R8C23D.F0 to     R8C23D.DI0 led_reg6_i (to clk_c)
                  --------
                   87.565   (27.5% logic, 72.5% route), 55 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to SLICE_573:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R8C23D.CLK clk_c
                  --------
                    4.162   (33.0% logic, 67.0% route), 1 logic levels.

Warning:   0.367MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "u3.clk_40khz" 39.330000 MHz ;
            4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 93.151ns (weighted slack = -9324.635ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.617ns  (27.2% logic, 72.8% route), 57 logic levels.

 Constraint Details:

     93.617ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 93.151ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19C.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19C.B0 to      R5C19C.F0 u2/u1/SLICE_1155
ROUTE         4     0.892      R5C19C.F0 to      R7C19A.A1 u2/u1/shift_reg_61[34]
CTOF_DEL    ---     0.452      R7C19A.A1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28C.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28C.B0 to     R10C28C.F0 u2/u1/SLICE_979
ROUTE         7     1.325     R10C28C.F0 to      R9C27C.D1 u2.u1.shift_reg_452[51]
CTOF_DEL    ---     0.452      R9C27C.D1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.617   (27.2% logic, 72.8% route), 57 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 93.119ns (weighted slack = -9321.432ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.585ns  (26.7% logic, 73.3% route), 56 logic levels.

 Constraint Details:

     93.585ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 93.119ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.697      R5C19A.F0 to      R7C19A.C1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19A.C1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28C.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28C.B0 to     R10C28C.F0 u2/u1/SLICE_979
ROUTE         7     1.325     R10C28C.F0 to      R9C27C.D1 u2.u1.shift_reg_452[51]
CTOF_DEL    ---     0.452      R9C27C.D1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.585   (26.7% logic, 73.3% route), 56 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 93.013ns (weighted slack = -9310.821ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.479ns  (27.2% logic, 72.8% route), 57 logic levels.

 Constraint Details:

     93.479ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 93.013ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19C.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19C.B0 to      R5C19C.F0 u2/u1/SLICE_1155
ROUTE         4     0.892      R5C19C.F0 to      R7C19A.A1 u2/u1/shift_reg_61[34]
CTOF_DEL    ---     0.452      R7C19A.A1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28A.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28A.B0 to     R10C28A.F0 SLICE_799
ROUTE         2     1.187     R10C28A.F0 to      R9C27C.B1 u3.data_6_14_8_.m1_N_10
CTOF_DEL    ---     0.452      R9C27C.B1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.479   (27.2% logic, 72.8% route), 57 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 92.981ns (weighted slack = -9307.618ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.447ns  (26.7% logic, 73.3% route), 56 logic levels.

 Constraint Details:

     93.447ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 92.981ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.697      R5C19A.F0 to      R7C19A.C1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19A.C1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28A.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28A.B0 to     R10C28A.F0 SLICE_799
ROUTE         2     1.187     R10C28A.F0 to      R9C27C.B1 u3.data_6_14_8_.m1_N_10
CTOF_DEL    ---     0.452      R9C27C.B1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.447   (26.7% logic, 73.3% route), 56 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 92.956ns (weighted slack = -9305.115ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.422ns  (27.2% logic, 72.8% route), 57 logic levels.

 Constraint Details:

     93.422ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 92.956ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19A.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19A.B0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.697      R5C19A.F0 to      R7C19A.C1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19A.C1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28C.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28C.B0 to     R10C28C.F0 u2/u1/SLICE_979
ROUTE         7     1.325     R10C28C.F0 to      R9C27C.D1 u2.u1.shift_reg_452[51]
CTOF_DEL    ---     0.452      R9C27C.D1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.422   (27.2% logic, 72.8% route), 57 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 92.934ns (weighted slack = -9302.913ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.400ns  (27.2% logic, 72.8% route), 57 logic levels.

 Constraint Details:

     93.400ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 92.934ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19C.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19C.B0 to      R5C19C.F0 u2/u1/SLICE_1155
ROUTE         4     0.892      R5C19C.F0 to      R7C19A.A1 u2/u1/shift_reg_61[34]
CTOF_DEL    ---     0.452      R7C19A.A1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.328     R13C25D.F1 to     R13C28A.D0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C28A.D0 to     R13C28A.F0 u2/u1/SLICE_1228
ROUTE         1     0.937     R13C28A.F0 to     R12C28C.A1 u2/u1/shift_reg_365_c1
CTOF_DEL    ---     0.452     R12C28C.A1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28C.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28C.B0 to     R10C28C.F0 u2/u1/SLICE_979
ROUTE         7     1.325     R10C28C.F0 to      R9C27C.D1 u2.u1.shift_reg_452[51]
CTOF_DEL    ---     0.452      R9C27C.D1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.400   (27.2% logic, 72.8% route), 57 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 92.924ns (weighted slack = -9301.912ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.390ns  (26.3% logic, 73.7% route), 55 logic levels.

 Constraint Details:

     93.390ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 92.924ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.923      R5C19A.F0 to      R7C19B.B1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19B.B1 to      R7C19B.F1 u2/u1/SLICE_1149
ROUTE         4     0.895      R7C19B.F1 to      R8C19D.A0 u2/u1/shift_reg_71[34]
CTOF_DEL    ---     0.452      R8C19D.A0 to      R8C19D.F0 u2/u1/SLICE_1142
ROUTE         6     1.788      R8C19D.F0 to     R10C18C.D0 u2/u1/shift_reg_84[33]
CTOF_DEL    ---     0.452     R10C18C.D0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28C.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28C.B0 to     R10C28C.F0 u2/u1/SLICE_979
ROUTE         7     1.325     R10C28C.F0 to      R9C27C.D1 u2.u1.shift_reg_452[51]
CTOF_DEL    ---     0.452      R9C27C.D1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.390   (26.3% logic, 73.7% route), 55 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 92.902ns (weighted slack = -9299.710ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.368ns  (26.7% logic, 73.3% route), 56 logic levels.

 Constraint Details:

     93.368ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 92.902ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.697      R5C19A.F0 to      R7C19A.C1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19A.C1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.328     R13C25D.F1 to     R13C28A.D0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C28A.D0 to     R13C28A.F0 u2/u1/SLICE_1228
ROUTE         1     0.937     R13C28A.F0 to     R12C28C.A1 u2/u1/shift_reg_365_c1
CTOF_DEL    ---     0.452     R12C28C.A1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28C.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28C.B0 to     R10C28C.F0 u2/u1/SLICE_979
ROUTE         7     1.325     R10C28C.F0 to      R9C27C.D1 u2.u1.shift_reg_452[51]
CTOF_DEL    ---     0.452      R9C27C.D1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.368   (26.7% logic, 73.3% route), 56 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 92.888ns (weighted slack = -9298.308ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.354ns  (27.2% logic, 72.8% route), 57 logic levels.

 Constraint Details:

     93.354ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 92.888ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.810      R8C17B.F0 to      R5C18C.B1 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18C.B1 to      R5C18C.F1 u2/u1/SLICE_1166
ROUTE         1     0.541      R5C18C.F1 to      R5C17D.D1 u2/u1/CO2_117_sx_0
CTOF_DEL    ---     0.452      R5C17D.D1 to      R5C17D.F1 u2/u1/SLICE_846
ROUTE         1     0.563      R5C17D.F1 to      R5C19B.D1 u2/u1/CO2_111
CTOF_DEL    ---     0.452      R5C19B.D1 to      R5C19B.F1 u2/u1/SLICE_1158
ROUTE         4     0.907      R5C19B.F1 to      R5C19C.B0 u2/u1/shift_reg_51[33]
CTOF_DEL    ---     0.452      R5C19C.B0 to      R5C19C.F0 u2/u1/SLICE_1155
ROUTE         4     0.892      R5C19C.F0 to      R7C19A.A1 u2/u1/shift_reg_61[34]
CTOF_DEL    ---     0.452      R7C19A.A1 to      R7C19A.F1 u2/u1/SLICE_1148
ROUTE         4     0.869      R7C19A.F1 to      R7C19B.A0 u2/u1/ANB1_107
CTOF_DEL    ---     0.452      R7C19B.A0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C27B.B1 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C27B.B1 to     R10C27B.F1 SLICE_919
ROUTE         9     1.062     R10C27B.F1 to      R9C27C.C1 u2.u1.shift_reg_452[50]
CTOF_DEL    ---     0.452      R9C27C.C1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.354   (27.2% logic, 72.8% route), 57 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.


Error: The following path exceeds requirements by 92.875ns (weighted slack = -9297.007ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/ch1_dat[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u3/data[13]  (to u3.clk_40khz +)

   Delay:              93.341ns  (26.8% logic, 73.2% route), 56 logic levels.

 Constraint Details:

     93.341ns physical path delay u1/SLICE_1346 to u3/SLICE_682 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 25.426ns)
      0.254ns delay constraint less
     -0.362ns skew and
      0.150ns DIN_SET requirement (totaling 0.466ns) by 92.875ns

 Physical Path Details:

      Data path u1/SLICE_1346 to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C16C.CLK to      R3C16C.Q1 u1/SLICE_1346 (from u1.clk_400khz)
ROUTE        11     5.263      R3C16C.Q1 to     R13C14B.B0 ch1_dat[1]
C0TOFCO_DE  ---     0.905     R13C14B.B0 to    R13C14B.FCO u2/SLICE_344
ROUTE         1     0.000    R13C14B.FCO to    R13C14C.FCI u2/un1_ch1_dat_1_cry_7
FCITOFCO_D  ---     0.146    R13C14C.FCI to    R13C14C.FCO u2/SLICE_343
ROUTE         1     0.000    R13C14C.FCO to    R13C14D.FCI u2/un1_ch1_dat_1_cry_9
FCITOF1_DE  ---     0.569    R13C14D.FCI to     R13C14D.F1 u2/SLICE_342
ROUTE         3     1.857     R13C14D.F1 to     R12C10D.B0 u2/un1_ch1_dat_1[11]
CTOF_DEL    ---     0.452     R12C10D.B0 to     R12C10D.F0 u2/SLICE_1244
ROUTE         1     2.012     R12C10D.F0 to     R13C11C.B1 u2/un1_lux_1_d1_58_0
C1TOFCO_DE  ---     0.786     R13C11C.B1 to    R13C11C.FCO u2/SLICE_498
ROUTE         1     0.000    R13C11C.FCO to    R13C11D.FCI u2/un1_lux_1_s0_m1_0_cry_12
FCITOFCO_D  ---     0.146    R13C11D.FCI to    R13C11D.FCO u2/SLICE_497
ROUTE         1     0.000    R13C11D.FCO to    R13C12A.FCI u2/un1_lux_1_s0_m1_0_cry_14
FCITOFCO_D  ---     0.146    R13C12A.FCI to    R13C12A.FCO u2/SLICE_496
ROUTE         1     0.000    R13C12A.FCO to    R13C12B.FCI u2/un1_lux_1_s0_m1_0_cry_16
FCITOFCO_D  ---     0.146    R13C12B.FCI to    R13C12B.FCO u2/SLICE_495
ROUTE         1     0.000    R13C12B.FCO to    R13C12C.FCI u2/un1_lux_1_s0_m1_0_cry_18
FCITOFCO_D  ---     0.146    R13C12C.FCI to    R13C12C.FCO u2/SLICE_494
ROUTE         1     0.000    R13C12C.FCO to    R13C12D.FCI u2/un1_lux_1_s0_m1_0_cry_20
FCITOFCO_D  ---     0.146    R13C12D.FCI to    R13C12D.FCO u2/SLICE_493
ROUTE         1     0.000    R13C12D.FCO to    R13C13A.FCI u2/un1_lux_1_s0_m1_0_cry_22
FCITOF1_DE  ---     0.569    R13C13A.FCI to     R13C13A.F1 u2/SLICE_492
ROUTE         1     1.473     R13C13A.F1 to     R12C16C.B1 u2/un1_lux_1_s0_m1_0_cry_23_0_S1
CTOF_DEL    ---     0.452     R12C16C.B1 to     R12C16C.F1 u2/SLICE_868
ROUTE         3     0.625     R12C16C.F1 to     R12C16B.B0 u2/un1_lux_1_s0_m1[26]
CTOF_DEL    ---     0.452     R12C16B.B0 to     R12C16B.F0 u2/SLICE_1163
ROUTE         1     1.347     R12C16B.F0 to     R10C17B.B0 u2/u1/shift_reg_0_1[34]
CTOF_DEL    ---     0.452     R10C17B.B0 to     R10C17B.F0 u2/u1/SLICE_848
ROUTE         1     0.384     R10C17B.F0 to     R10C17B.C1 u2/u1/shift_reg_0_2[34]
CTOF_DEL    ---     0.452     R10C17B.C1 to     R10C17B.F1 u2/u1/SLICE_848
ROUTE         2     2.295     R10C17B.F1 to     R10C17D.B1 u2/u1/shift_reg_27_a0_RNIN15GG1[34]
CTOF_DEL    ---     0.452     R10C17D.B1 to     R10C17D.F1 u2/u1/SLICE_1164
ROUTE         2     1.042     R10C17D.F1 to      R8C17B.C0 u2/u1/shift_reg_27[34]
CTOF_DEL    ---     0.452      R8C17B.C0 to      R8C17B.F0 u2/u1/SLICE_847
ROUTE         3     1.934      R8C17B.F0 to      R5C18B.C0 u2/u1/ANB1_120
CTOF_DEL    ---     0.452      R5C18B.C0 to      R5C18B.F0 u2/u1/SLICE_1212
ROUTE         2     0.896      R5C18B.F0 to      R5C19A.B1 u2/u1/shift_reg_41[33]
CTOF_DEL    ---     0.452      R5C19A.B1 to      R5C19A.F1 u2/u1/SLICE_1156
ROUTE         4     1.606      R5C19A.F1 to      R5C19A.A0 u2/u1/ANB1_114
CTOF_DEL    ---     0.452      R5C19A.A0 to      R5C19A.F0 u2/u1/SLICE_1156
ROUTE         4     0.923      R5C19A.F0 to      R7C19B.B1 u2/u1/shift_reg_61[33]
CTOF_DEL    ---     0.452      R7C19B.B1 to      R7C19B.F1 u2/u1/SLICE_1149
ROUTE         4     0.399      R7C19B.F1 to      R7C19B.C0 u2/u1/shift_reg_71[34]
CTOF_DEL    ---     0.452      R7C19B.C0 to      R7C19B.F0 u2/u1/SLICE_1149
ROUTE         4     1.391      R7C19B.F0 to     R10C18C.D1 u2/u1/ANB1_103
CTOF_DEL    ---     0.452     R10C18C.D1 to     R10C18C.F1 u2/u1/SLICE_1138
ROUTE         3     0.392     R10C18C.F1 to     R10C18C.C0 u2/u1/CO1_103
CTOF_DEL    ---     0.452     R10C18C.C0 to     R10C18C.F0 u2/u1/SLICE_1138
ROUTE         5     1.608     R10C18C.F0 to     R12C18A.B0 u2/u1/ANB1_98
CTOF_DEL    ---     0.452     R12C18A.B0 to     R12C18A.F0 u2/u1/SLICE_1129
ROUTE        10     1.247     R12C18A.F0 to      R9C18B.A0 u2/u1/CO0_95
CTOF_DEL    ---     0.452      R9C18B.A0 to      R9C18B.F0 u2/SLICE_648
ROUTE         1     1.369      R9C18B.F0 to     R13C18B.B1 u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_0[37]
CTOF_DEL    ---     0.452     R13C18B.B1 to     R13C18B.F1 u2/u1/SLICE_1126
ROUTE         3     1.408     R13C18B.F1 to     R12C19C.B0 u2/u1/shift_reg_110_RNIPJKQR2[34]
CTOF_DEL    ---     0.452     R12C19C.B0 to     R12C19C.F0 u2/u1/SLICE_942
ROUTE         7     1.542     R12C19C.F0 to     R13C19A.M0 u2/u1/CO2_85
MTOOFX_DEL  ---     0.345     R13C19A.M0 to   R13C19A.OFX0 u2/u1/shift_reg_145cf0_RNI4P3MT5[38]/SLICE_747
ROUTE         9     2.422   R13C19A.OFX0 to     R14C19B.A1 u2/u1/CO2_80
CTOF_DEL    ---     0.452     R14C19B.A1 to     R14C19B.F1 u2/u1/SLICE_1168
ROUTE         1     1.223     R14C19B.F1 to     R15C19A.A1 u2/u1/shift_reg_180cf1_N_2L1_0
CTOOFX_DEL  ---     0.661     R15C19A.A1 to   R15C19A.OFX0 u2/u1/shift_reg_180[38]/SLICE_732
ROUTE         5     1.760   R15C19A.OFX0 to     R16C21C.B0 u2/u1/shift_reg_180[38]
CTOF_DEL    ---     0.452     R16C21C.B0 to     R16C21C.F0 u2/u1/SLICE_1094
ROUTE         7     2.053     R16C21C.F0 to     R15C21B.A0 u2/u1/CO2_69
CTOF_DEL    ---     0.452     R15C21B.A0 to     R15C21B.F0 u2/u1/SLICE_835
ROUTE         7     0.920     R15C21B.F0 to     R16C21B.D0 u2/u1/CO0_68
CTOF_DEL    ---     0.452     R16C21B.D0 to     R16C21B.F0 u2/u1/SLICE_833
ROUTE         7     3.305     R16C21B.F0 to     R16C22C.D1 u2/u1/CO0_62
CTOF_DEL    ---     0.452     R16C22C.D1 to     R16C22C.F1 u2/u1/SLICE_964
ROUTE         6     0.902     R16C22C.F1 to     R17C22A.A0 u2/u1/shift_reg_218[38]
CTOF_DEL    ---     0.452     R17C22A.A0 to     R17C22A.F0 u2/u1/SLICE_948
ROUTE         1     1.909     R17C22A.F0 to     R16C22A.B0 u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[37]
CTOF_DEL    ---     0.452     R16C22A.B0 to     R16C22A.F0 u2/u1/SLICE_866
ROUTE         3     0.900     R16C22A.F0 to     R16C22A.B1 u2/u1/CO2_49
CTOF_DEL    ---     0.452     R16C22A.B1 to     R16C22A.F1 u2/u1/SLICE_866
ROUTE         2     0.685     R16C22A.F1 to     R16C23D.C0 u2/u1/CO1_46
CTOF_DEL    ---     0.452     R16C23D.C0 to     R16C23D.F0 u2/u1/SLICE_852
ROUTE         4     0.632     R16C23D.F0 to     R16C23B.B1 u2/u1/SUM1_31_3_1
CTOF_DEL    ---     0.452     R16C23B.B1 to     R16C23B.F1 u2/u1/SLICE_1051
ROUTE         4     0.862     R16C23B.F1 to     R16C23B.A0 u2/u1/CO0_40
CTOF_DEL    ---     0.452     R16C23B.A0 to     R16C23B.F0 u2/u1/SLICE_1051
ROUTE         6     0.938     R16C23B.F0 to     R14C23C.B1 u2/u1/shift_reg_284[38]
CTOF_DEL    ---     0.452     R14C23C.B1 to     R14C23C.F1 u2/u1/SLICE_785
ROUTE         6     2.070     R14C23C.F1 to     R13C25D.B1 u2/u1/CO0_32
CTOF_DEL    ---     0.452     R13C25D.B1 to     R13C25D.F1 u2/u1/SLICE_1034
ROUTE         6     1.238     R13C25D.F1 to     R13C27B.A0 u2/u1/un1_shift_reg_axb0_3
CTOF_DEL    ---     0.452     R13C27B.A0 to     R13C27B.F0 u2/u1/SLICE_784
ROUTE         1     1.244     R13C27B.F0 to     R12C28C.B1 u2/u1/un1_shift_reg_c3_d
CTOF_DEL    ---     0.452     R12C28C.B1 to     R12C28C.F1 u2/u1/SLICE_1015
ROUTE         6     0.897     R12C28C.F1 to     R12C28A.A1 u2/u1/shift_reg_365[46]
CTOF_DEL    ---     0.452     R12C28A.A1 to     R12C28A.F1 u2/u1/SLICE_992
ROUTE        11     2.209     R12C28A.F1 to     R13C30D.D0 u2.u1.CO0_11
CTOF_DEL    ---     0.452     R13C30D.D0 to     R13C30D.F0 u2/u1/SLICE_1004
ROUTE         1     1.632     R13C30D.F0 to     R10C29A.D1 u2/u1/un1_shift_reg_4_c3_0_a1_a0
CTOF_DEL    ---     0.452     R10C29A.D1 to     R10C29A.F1 u2/u1/SLICE_986
ROUTE         2     0.862     R10C29A.F1 to     R10C29B.A0 u2/u1/un1_shift_reg_4_c3_0_a1_0
CTOF_DEL    ---     0.452     R10C29B.A0 to     R10C29B.F0 u2/u1/SLICE_990
ROUTE         3     0.917     R10C29B.F0 to     R10C28C.B0 u2.u1._l30.un1_shift_reg_4
CTOF_DEL    ---     0.452     R10C28C.B0 to     R10C28C.F0 u2/u1/SLICE_979
ROUTE         7     1.325     R10C28C.F0 to      R9C27C.D1 u2.u1.shift_reg_452[51]
CTOF_DEL    ---     0.452      R9C27C.D1 to      R9C27C.F1 SLICE_904
ROUTE        11     3.280      R9C27C.F1 to      R8C26C.B0 u2.u1._l31.shift_reg_480[48]
CTOF_DEL    ---     0.452      R8C26C.B0 to      R8C26C.F0 SLICE_1313
ROUTE         2     1.035      R8C26C.F0 to      R7C26D.C1 u3/N_12_0
CTOOFX_DEL  ---     0.661      R7C26D.C1 to    R7C26D.OFX0 u3/data_12_7_am_RNO_0[13]/SLICE_730
ROUTE         1     0.882    R7C26D.OFX0 to      R7C25C.B0 u3/data_12_7_am_RNO_0[13]
CTOF_DEL    ---     0.452      R7C25C.B0 to      R7C25C.F0 u3/SLICE_1311
ROUTE         1     1.252      R7C25C.F0 to      R5C27C.A0 u3/data_12_7_am_RNO[13]
CTOOFX_DEL  ---     0.661      R5C27C.A0 to    R5C27C.OFX0 u3/SLICE_682
ROUTE         1     0.000    R5C27C.OFX0 to     R5C27C.DI0 u3/data_12[13] (to u3.clk_40khz)
                  --------
                   93.341   (26.8% logic, 73.2% route), 56 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1346:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.409     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     2.660      R2C16C.Q0 to     R3C16C.CLK u1.clk_400khz
                  --------
                    7.231   (24.6% logic, 75.4% route), 2 logic levels.

      Destination Clock Path clk to u3/SLICE_682:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.372         C1.PAD to       C1.PADDI clk
ROUTE        59     2.790       C1.PADDI to     R13C2A.CLK clk_c
REG_DEL     ---     0.409     R13C2A.CLK to      R13C2A.Q0 u3/SLICE_667
ROUTE        20     3.022      R13C2A.Q0 to     R5C27C.CLK u3.clk_40khz
                  --------
                    7.593   (23.5% logic, 76.5% route), 2 logic levels.

Warning:   0.107MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "u1.clk_400khz" 158.907000 MHz ;
            4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 6.516ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_delay[6]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/cnt_delay[23]  (to u1.clk_400khz +)

   Delay:              12.659ns  (49.7% logic, 50.3% route), 25 logic levels.

 Constraint Details:

     12.659ns physical path delay u1/SLICE_531 to u1/SLICE_522 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.516ns

 Physical Path Details:

      Data path u1/SLICE_531 to u1/SLICE_522:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409      R3C2D.CLK to       R3C2D.Q1 u1/SLICE_531 (from u1.clk_400khz)
ROUTE         2     1.331       R3C2D.Q1 to       R4C3A.A1 u1/cnt_delay[6]
C1TOFCO_DE  ---     0.786       R4C3A.A1 to      R4C3A.FCO u1/SLICE_515
ROUTE         1     0.000      R4C3A.FCO to      R4C3B.FCI u1/un1_cnt_delay_cry_6
FCITOFCO_D  ---     0.146      R4C3B.FCI to      R4C3B.FCO u1/SLICE_514
ROUTE         1     0.000      R4C3B.FCO to      R4C3C.FCI u1/un1_cnt_delay_cry_8
FCITOFCO_D  ---     0.146      R4C3C.FCI to      R4C3C.FCO u1/SLICE_513
ROUTE         1     0.000      R4C3C.FCO to      R4C3D.FCI u1/un1_cnt_delay_cry_10
FCITOFCO_D  ---     0.146      R4C3D.FCI to      R4C3D.FCO u1/SLICE_512
ROUTE         1     0.000      R4C3D.FCO to      R4C4A.FCI u1/un1_cnt_delay_cry_12
FCITOFCO_D  ---     0.146      R4C4A.FCI to      R4C4A.FCO u1/SLICE_511
ROUTE         1     0.000      R4C4A.FCO to      R4C4B.FCI u1/un1_cnt_delay_cry_14
FCITOFCO_D  ---     0.146      R4C4B.FCI to      R4C4B.FCO u1/SLICE_510
ROUTE         1     0.000      R4C4B.FCO to      R4C4C.FCI u1/un1_cnt_delay_cry_16
FCITOFCO_D  ---     0.146      R4C4C.FCI to      R4C4C.FCO u1/SLICE_509
ROUTE         1     0.000      R4C4C.FCO to      R4C4D.FCI u1/un1_cnt_delay_cry_18
FCITOFCO_D  ---     0.146      R4C4D.FCI to      R4C4D.FCO u1/SLICE_508
ROUTE         1     0.000      R4C4D.FCO to      R4C5A.FCI u1/un1_cnt_delay_cry_20
FCITOFCO_D  ---     0.146      R4C5A.FCI to      R4C5A.FCO u1/SLICE_507
ROUTE         1     0.000      R4C5A.FCO to      R4C5B.FCI u1/un1_cnt_delay_cry_22
FCITOF1_DE  ---     0.569      R4C5B.FCI to       R4C5B.F1 u1/SLICE_506
ROUTE         3     2.343       R4C5B.F1 to      R9C15D.C1 u1/un1_cnt_delay_cry_23
CTOF_DEL    ---     0.452      R9C15D.C1 to      R9C15D.F1 u1/SLICE_1344
ROUTE        25     2.692      R9C15D.F1 to       R3C2A.B1 u1/N_440
C1TOFCO_DE  ---     0.786       R3C2A.B1 to      R3C2A.FCO u1/SLICE_505
ROUTE         1     0.000      R3C2A.FCO to      R3C2B.FCI u1/cnt_delay_cry[0]
FCITOFCO_D  ---     0.146      R3C2B.FCI to      R3C2B.FCO u1/SLICE_533
ROUTE         1     0.000      R3C2B.FCO to      R3C2C.FCI u1/cnt_delay_cry[2]
FCITOFCO_D  ---     0.146      R3C2C.FCI to      R3C2C.FCO u1/SLICE_532
ROUTE         1     0.000      R3C2C.FCO to      R3C2D.FCI u1/cnt_delay_cry[4]
FCITOFCO_D  ---     0.146      R3C2D.FCI to      R3C2D.FCO u1/SLICE_531
ROUTE         1     0.000      R3C2D.FCO to      R3C3A.FCI u1/cnt_delay_cry[6]
FCITOFCO_D  ---     0.146      R3C3A.FCI to      R3C3A.FCO u1/SLICE_530
ROUTE         1     0.000      R3C3A.FCO to      R3C3B.FCI u1/cnt_delay_cry[8]
FCITOFCO_D  ---     0.146      R3C3B.FCI to      R3C3B.FCO u1/SLICE_529
ROUTE         1     0.000      R3C3B.FCO to      R3C3C.FCI u1/cnt_delay_cry[10]
FCITOFCO_D  ---     0.146      R3C3C.FCI to      R3C3C.FCO u1/SLICE_528
ROUTE         1     0.000      R3C3C.FCO to      R3C3D.FCI u1/cnt_delay_cry[12]
FCITOFCO_D  ---     0.146      R3C3D.FCI to      R3C3D.FCO u1/SLICE_527
ROUTE         1     0.000      R3C3D.FCO to      R3C4A.FCI u1/cnt_delay_cry[14]
FCITOFCO_D  ---     0.146      R3C4A.FCI to      R3C4A.FCO u1/SLICE_526
ROUTE         1     0.000      R3C4A.FCO to      R3C4B.FCI u1/cnt_delay_cry[16]
FCITOFCO_D  ---     0.146      R3C4B.FCI to      R3C4B.FCO u1/SLICE_525
ROUTE         1     0.000      R3C4B.FCO to      R3C4C.FCI u1/cnt_delay_cry[18]
FCITOFCO_D  ---     0.146      R3C4C.FCI to      R3C4C.FCO u1/SLICE_524
ROUTE         1     0.000      R3C4C.FCO to      R3C4D.FCI u1/cnt_delay_cry[20]
FCITOFCO_D  ---     0.146      R3C4D.FCI to      R3C4D.FCO u1/SLICE_523
ROUTE         1     0.000      R3C4D.FCO to      R3C5A.FCI u1/cnt_delay_cry[22]
FCITOF0_DE  ---     0.517      R3C5A.FCI to       R3C5A.F0 u1/SLICE_522
ROUTE         1     0.000       R3C5A.F0 to      R3C5A.DI0 u1/cnt_delay_s[23] (to u1.clk_400khz)
                  --------
                   12.659   (49.7% logic, 50.3% route), 25 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_531:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to      R3C2D.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_522:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to      R3C5A.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.489ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_delay[6]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/cnt_delay[23]  (to u1.clk_400khz +)

   Delay:              12.632ns  (49.6% logic, 50.4% route), 24 logic levels.

 Constraint Details:

     12.632ns physical path delay u1/SLICE_531 to u1/SLICE_522 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.489ns

 Physical Path Details:

      Data path u1/SLICE_531 to u1/SLICE_522:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409      R3C2D.CLK to       R3C2D.Q1 u1/SLICE_531 (from u1.clk_400khz)
ROUTE         2     1.331       R3C2D.Q1 to       R4C3A.A1 u1/cnt_delay[6]
C1TOFCO_DE  ---     0.786       R4C3A.A1 to      R4C3A.FCO u1/SLICE_515
ROUTE         1     0.000      R4C3A.FCO to      R4C3B.FCI u1/un1_cnt_delay_cry_6
FCITOFCO_D  ---     0.146      R4C3B.FCI to      R4C3B.FCO u1/SLICE_514
ROUTE         1     0.000      R4C3B.FCO to      R4C3C.FCI u1/un1_cnt_delay_cry_8
FCITOFCO_D  ---     0.146      R4C3C.FCI to      R4C3C.FCO u1/SLICE_513
ROUTE         1     0.000      R4C3C.FCO to      R4C3D.FCI u1/un1_cnt_delay_cry_10
FCITOFCO_D  ---     0.146      R4C3D.FCI to      R4C3D.FCO u1/SLICE_512
ROUTE         1     0.000      R4C3D.FCO to      R4C4A.FCI u1/un1_cnt_delay_cry_12
FCITOFCO_D  ---     0.146      R4C4A.FCI to      R4C4A.FCO u1/SLICE_511
ROUTE         1     0.000      R4C4A.FCO to      R4C4B.FCI u1/un1_cnt_delay_cry_14
FCITOFCO_D  ---     0.146      R4C4B.FCI to      R4C4B.FCO u1/SLICE_510
ROUTE         1     0.000      R4C4B.FCO to      R4C4C.FCI u1/un1_cnt_delay_cry_16
FCITOFCO_D  ---     0.146      R4C4C.FCI to      R4C4C.FCO u1/SLICE_509
ROUTE         1     0.000      R4C4C.FCO to      R4C4D.FCI u1/un1_cnt_delay_cry_18
FCITOFCO_D  ---     0.146      R4C4D.FCI to      R4C4D.FCO u1/SLICE_508
ROUTE         1     0.000      R4C4D.FCO to      R4C5A.FCI u1/un1_cnt_delay_cry_20
FCITOFCO_D  ---     0.146      R4C5A.FCI to      R4C5A.FCO u1/SLICE_507
ROUTE         1     0.000      R4C5A.FCO to      R4C5B.FCI u1/un1_cnt_delay_cry_22
FCITOF1_DE  ---     0.569      R4C5B.FCI to       R4C5B.F1 u1/SLICE_506
ROUTE         3     2.343       R4C5B.F1 to      R9C15D.C1 u1/un1_cnt_delay_cry_23
CTOF_DEL    ---     0.452      R9C15D.C1 to      R9C15D.F1 u1/SLICE_1344
ROUTE        25     2.692      R9C15D.F1 to       R3C2B.B0 u1/N_440
C0TOFCO_DE  ---     0.905       R3C2B.B0 to      R3C2B.FCO u1/SLICE_533
ROUTE         1     0.000      R3C2B.FCO to      R3C2C.FCI u1/cnt_delay_cry[2]
FCITOFCO_D  ---     0.146      R3C2C.FCI to      R3C2C.FCO u1/SLICE_532
ROUTE         1     0.000      R3C2C.FCO to      R3C2D.FCI u1/cnt_delay_cry[4]
FCITOFCO_D  ---     0.146      R3C2D.FCI to      R3C2D.FCO u1/SLICE_531
ROUTE         1     0.000      R3C2D.FCO to      R3C3A.FCI u1/cnt_delay_cry[6]
FCITOFCO_D  ---     0.146      R3C3A.FCI to      R3C3A.FCO u1/SLICE_530
ROUTE         1     0.000      R3C3A.FCO to      R3C3B.FCI u1/cnt_delay_cry[8]
FCITOFCO_D  ---     0.146      R3C3B.FCI to      R3C3B.FCO u1/SLICE_529
ROUTE         1     0.000      R3C3B.FCO to      R3C3C.FCI u1/cnt_delay_cry[10]
FCITOFCO_D  ---     0.146      R3C3C.FCI to      R3C3C.FCO u1/SLICE_528
ROUTE         1     0.000      R3C3C.FCO to      R3C3D.FCI u1/cnt_delay_cry[12]
FCITOFCO_D  ---     0.146      R3C3D.FCI to      R3C3D.FCO u1/SLICE_527
ROUTE         1     0.000      R3C3D.FCO to      R3C4A.FCI u1/cnt_delay_cry[14]
FCITOFCO_D  ---     0.146      R3C4A.FCI to      R3C4A.FCO u1/SLICE_526
ROUTE         1     0.000      R3C4A.FCO to      R3C4B.FCI u1/cnt_delay_cry[16]
FCITOFCO_D  ---     0.146      R3C4B.FCI to      R3C4B.FCO u1/SLICE_525
ROUTE         1     0.000      R3C4B.FCO to      R3C4C.FCI u1/cnt_delay_cry[18]
FCITOFCO_D  ---     0.146      R3C4C.FCI to      R3C4C.FCO u1/SLICE_524
ROUTE         1     0.000      R3C4C.FCO to      R3C4D.FCI u1/cnt_delay_cry[20]
FCITOFCO_D  ---     0.146      R3C4D.FCI to      R3C4D.FCO u1/SLICE_523
ROUTE         1     0.000      R3C4D.FCO to      R3C5A.FCI u1/cnt_delay_cry[22]
FCITOF0_DE  ---     0.517      R3C5A.FCI to       R3C5A.F0 u1/SLICE_522
ROUTE         1     0.000       R3C5A.F0 to      R3C5A.DI0 u1/cnt_delay_s[23] (to u1.clk_400khz)
                  --------
                   12.632   (49.6% logic, 50.4% route), 24 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_531:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to      R3C2D.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_522:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to      R3C5A.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.447ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_l[0]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/ch1_dat_pipe_79  (to u1.clk_400khz +)

   Delay:              12.590ns  (33.4% logic, 66.6% route), 12 logic levels.

 Constraint Details:

     12.590ns physical path delay u1/SLICE_1213 to u2/SLICE_323 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.447ns

 Physical Path Details:

      Data path u1/SLICE_1213 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R5C13A.CLK to      R5C13A.Q0 u1/SLICE_1213 (from u1.clk_400khz)
ROUTE        53     6.749      R5C13A.Q0 to     R20C21A.A1 u1.dat_l[0]
C1TOFCO_DE  ---     0.786     R20C21A.A1 to    R20C21A.FCO u2/SLICE_355
ROUTE         1     0.000    R20C21A.FCO to    R20C21B.FCI u2/un1_ch1_dat_0_7_cry_0
FCITOFCO_D  ---     0.146    R20C21B.FCI to    R20C21B.FCO u2/SLICE_354
ROUTE         1     0.000    R20C21B.FCO to    R20C21C.FCI u2/un1_ch1_dat_0_7_cry_2
FCITOFCO_D  ---     0.146    R20C21C.FCI to    R20C21C.FCO u2/SLICE_353
ROUTE         1     0.000    R20C21C.FCO to    R20C21D.FCI u2/un1_ch1_dat_0_7_cry_4
FCITOF0_DE  ---     0.517    R20C21D.FCI to     R20C21D.F0 u2/SLICE_352
ROUTE         1     1.633     R20C21D.F0 to     R19C22D.B0 u2/un1_ch1_dat_0_7_0[13]
C0TOFCO_DE  ---     0.905     R19C22D.B0 to    R19C22D.FCO u2/SLICE_329
ROUTE         1     0.000    R19C22D.FCO to    R19C23A.FCI u2/un1_ch1_dat_0_4_cry_14
FCITOFCO_D  ---     0.146    R19C23A.FCI to    R19C23A.FCO u2/SLICE_328
ROUTE         1     0.000    R19C23A.FCO to    R19C23B.FCI u2/un1_ch1_dat_0_4_cry_16
FCITOFCO_D  ---     0.146    R19C23B.FCI to    R19C23B.FCO u2/SLICE_327
ROUTE         1     0.000    R19C23B.FCO to    R19C23C.FCI u2/un1_ch1_dat_0_4_cry_18
FCITOFCO_D  ---     0.146    R19C23C.FCI to    R19C23C.FCO u2/SLICE_326
ROUTE         1     0.000    R19C23C.FCO to    R19C23D.FCI u2/un1_ch1_dat_0_4_cry_20
FCITOFCO_D  ---     0.146    R19C23D.FCI to    R19C23D.FCO u2/SLICE_325
ROUTE         1     0.000    R19C23D.FCO to    R19C24A.FCI u2/un1_ch1_dat_0_4_cry_22
FCITOFCO_D  ---     0.146    R19C24A.FCI to    R19C24A.FCO u2/SLICE_324
ROUTE         1     0.000    R19C24A.FCO to    R19C24B.FCI u2/un1_ch1_dat_0_4_cry_24
FCITOF1_DE  ---     0.569    R19C24B.FCI to     R19C24B.F1 u2/SLICE_323
ROUTE         1     0.000     R19C24B.F1 to    R19C24B.DI1 u2/un1_ch1_dat_0_4_0[26] (to u1.clk_400khz)
                  --------
                   12.590   (33.4% logic, 66.6% route), 12 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1213:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to     R5C13A.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to    R19C24B.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.436ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_l[0]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/ch1_dat_pipe_79  (to u1.clk_400khz +)

   Delay:              12.579ns  (33.5% logic, 66.5% route), 12 logic levels.

 Constraint Details:

     12.579ns physical path delay u1/SLICE_1213 to u2/SLICE_323 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.436ns

 Physical Path Details:

      Data path u1/SLICE_1213 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R5C13A.CLK to      R5C13A.Q0 u1/SLICE_1213 (from u1.clk_400khz)
ROUTE        53     6.749      R5C13A.Q0 to     R20C21A.A1 u1.dat_l[0]
C1TOFCO_DE  ---     0.786     R20C21A.A1 to    R20C21A.FCO u2/SLICE_355
ROUTE         1     0.000    R20C21A.FCO to    R20C21B.FCI u2/un1_ch1_dat_0_7_cry_0
FCITOFCO_D  ---     0.146    R20C21B.FCI to    R20C21B.FCO u2/SLICE_354
ROUTE         1     0.000    R20C21B.FCO to    R20C21C.FCI u2/un1_ch1_dat_0_7_cry_2
FCITOFCO_D  ---     0.146    R20C21C.FCI to    R20C21C.FCO u2/SLICE_353
ROUTE         1     0.000    R20C21C.FCO to    R20C21D.FCI u2/un1_ch1_dat_0_7_cry_4
FCITOFCO_D  ---     0.146    R20C21D.FCI to    R20C21D.FCO u2/SLICE_352
ROUTE         1     0.000    R20C21D.FCO to    R20C22A.FCI u2/un1_ch1_dat_0_7_cry_6
FCITOFCO_D  ---     0.146    R20C22A.FCI to    R20C22A.FCO u2/SLICE_351
ROUTE         1     0.000    R20C22A.FCO to    R20C22B.FCI u2/un1_ch1_dat_0_7_cry_8
FCITOFCO_D  ---     0.146    R20C22B.FCI to    R20C22B.FCO u2/SLICE_350
ROUTE         1     0.000    R20C22B.FCO to    R20C22C.FCI u2/un1_ch1_dat_0_7_cry_10
FCITOFCO_D  ---     0.146    R20C22C.FCI to    R20C22C.FCO u2/SLICE_349
ROUTE         1     0.000    R20C22C.FCO to    R20C22D.FCI u2/un1_ch1_dat_0_7_cry_12
FCITOF0_DE  ---     0.517    R20C22D.FCI to     R20C22D.F0 u2/SLICE_348
ROUTE         1     1.622     R20C22D.F0 to     R19C23D.B0 u2/un1_ch1_dat_0_7_0[21]
C0TOFCO_DE  ---     0.905     R19C23D.B0 to    R19C23D.FCO u2/SLICE_325
ROUTE         1     0.000    R19C23D.FCO to    R19C24A.FCI u2/un1_ch1_dat_0_4_cry_22
FCITOFCO_D  ---     0.146    R19C24A.FCI to    R19C24A.FCO u2/SLICE_324
ROUTE         1     0.000    R19C24A.FCO to    R19C24B.FCI u2/un1_ch1_dat_0_4_cry_24
FCITOF1_DE  ---     0.569    R19C24B.FCI to     R19C24B.F1 u2/SLICE_323
ROUTE         1     0.000     R19C24B.F1 to    R19C24B.DI1 u2/un1_ch1_dat_0_4_0[26] (to u1.clk_400khz)
                  --------
                   12.579   (33.5% logic, 66.5% route), 12 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1213:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to     R5C13A.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to    R19C24B.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.422ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_delay[6]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/cnt_delay[22]  (to u1.clk_400khz +)

   Delay:              12.565ns  (49.3% logic, 50.7% route), 24 logic levels.

 Constraint Details:

     12.565ns physical path delay u1/SLICE_531 to u1/SLICE_523 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.422ns

 Physical Path Details:

      Data path u1/SLICE_531 to u1/SLICE_523:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409      R3C2D.CLK to       R3C2D.Q1 u1/SLICE_531 (from u1.clk_400khz)
ROUTE         2     1.331       R3C2D.Q1 to       R4C3A.A1 u1/cnt_delay[6]
C1TOFCO_DE  ---     0.786       R4C3A.A1 to      R4C3A.FCO u1/SLICE_515
ROUTE         1     0.000      R4C3A.FCO to      R4C3B.FCI u1/un1_cnt_delay_cry_6
FCITOFCO_D  ---     0.146      R4C3B.FCI to      R4C3B.FCO u1/SLICE_514
ROUTE         1     0.000      R4C3B.FCO to      R4C3C.FCI u1/un1_cnt_delay_cry_8
FCITOFCO_D  ---     0.146      R4C3C.FCI to      R4C3C.FCO u1/SLICE_513
ROUTE         1     0.000      R4C3C.FCO to      R4C3D.FCI u1/un1_cnt_delay_cry_10
FCITOFCO_D  ---     0.146      R4C3D.FCI to      R4C3D.FCO u1/SLICE_512
ROUTE         1     0.000      R4C3D.FCO to      R4C4A.FCI u1/un1_cnt_delay_cry_12
FCITOFCO_D  ---     0.146      R4C4A.FCI to      R4C4A.FCO u1/SLICE_511
ROUTE         1     0.000      R4C4A.FCO to      R4C4B.FCI u1/un1_cnt_delay_cry_14
FCITOFCO_D  ---     0.146      R4C4B.FCI to      R4C4B.FCO u1/SLICE_510
ROUTE         1     0.000      R4C4B.FCO to      R4C4C.FCI u1/un1_cnt_delay_cry_16
FCITOFCO_D  ---     0.146      R4C4C.FCI to      R4C4C.FCO u1/SLICE_509
ROUTE         1     0.000      R4C4C.FCO to      R4C4D.FCI u1/un1_cnt_delay_cry_18
FCITOFCO_D  ---     0.146      R4C4D.FCI to      R4C4D.FCO u1/SLICE_508
ROUTE         1     0.000      R4C4D.FCO to      R4C5A.FCI u1/un1_cnt_delay_cry_20
FCITOFCO_D  ---     0.146      R4C5A.FCI to      R4C5A.FCO u1/SLICE_507
ROUTE         1     0.000      R4C5A.FCO to      R4C5B.FCI u1/un1_cnt_delay_cry_22
FCITOF1_DE  ---     0.569      R4C5B.FCI to       R4C5B.F1 u1/SLICE_506
ROUTE         3     2.343       R4C5B.F1 to      R9C15D.C1 u1/un1_cnt_delay_cry_23
CTOF_DEL    ---     0.452      R9C15D.C1 to      R9C15D.F1 u1/SLICE_1344
ROUTE        25     2.692      R9C15D.F1 to       R3C2A.B1 u1/N_440
C1TOFCO_DE  ---     0.786       R3C2A.B1 to      R3C2A.FCO u1/SLICE_505
ROUTE         1     0.000      R3C2A.FCO to      R3C2B.FCI u1/cnt_delay_cry[0]
FCITOFCO_D  ---     0.146      R3C2B.FCI to      R3C2B.FCO u1/SLICE_533
ROUTE         1     0.000      R3C2B.FCO to      R3C2C.FCI u1/cnt_delay_cry[2]
FCITOFCO_D  ---     0.146      R3C2C.FCI to      R3C2C.FCO u1/SLICE_532
ROUTE         1     0.000      R3C2C.FCO to      R3C2D.FCI u1/cnt_delay_cry[4]
FCITOFCO_D  ---     0.146      R3C2D.FCI to      R3C2D.FCO u1/SLICE_531
ROUTE         1     0.000      R3C2D.FCO to      R3C3A.FCI u1/cnt_delay_cry[6]
FCITOFCO_D  ---     0.146      R3C3A.FCI to      R3C3A.FCO u1/SLICE_530
ROUTE         1     0.000      R3C3A.FCO to      R3C3B.FCI u1/cnt_delay_cry[8]
FCITOFCO_D  ---     0.146      R3C3B.FCI to      R3C3B.FCO u1/SLICE_529
ROUTE         1     0.000      R3C3B.FCO to      R3C3C.FCI u1/cnt_delay_cry[10]
FCITOFCO_D  ---     0.146      R3C3C.FCI to      R3C3C.FCO u1/SLICE_528
ROUTE         1     0.000      R3C3C.FCO to      R3C3D.FCI u1/cnt_delay_cry[12]
FCITOFCO_D  ---     0.146      R3C3D.FCI to      R3C3D.FCO u1/SLICE_527
ROUTE         1     0.000      R3C3D.FCO to      R3C4A.FCI u1/cnt_delay_cry[14]
FCITOFCO_D  ---     0.146      R3C4A.FCI to      R3C4A.FCO u1/SLICE_526
ROUTE         1     0.000      R3C4A.FCO to      R3C4B.FCI u1/cnt_delay_cry[16]
FCITOFCO_D  ---     0.146      R3C4B.FCI to      R3C4B.FCO u1/SLICE_525
ROUTE         1     0.000      R3C4B.FCO to      R3C4C.FCI u1/cnt_delay_cry[18]
FCITOFCO_D  ---     0.146      R3C4C.FCI to      R3C4C.FCO u1/SLICE_524
ROUTE         1     0.000      R3C4C.FCO to      R3C4D.FCI u1/cnt_delay_cry[20]
FCITOF1_DE  ---     0.569      R3C4D.FCI to       R3C4D.F1 u1/SLICE_523
ROUTE         1     0.000       R3C4D.F1 to      R3C4D.DI1 u1/cnt_delay_s[22] (to u1.clk_400khz)
                  --------
                   12.565   (49.3% logic, 50.7% route), 24 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_531:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to      R3C2D.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_523:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to      R3C4D.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.416ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_l[0]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/ch1_dat_pipe_79  (to u1.clk_400khz +)

   Delay:              12.559ns  (33.5% logic, 66.5% route), 12 logic levels.

 Constraint Details:

     12.559ns physical path delay u1/SLICE_1213 to u2/SLICE_323 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.416ns

 Physical Path Details:

      Data path u1/SLICE_1213 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R5C13A.CLK to      R5C13A.Q0 u1/SLICE_1213 (from u1.clk_400khz)
ROUTE        53     6.749      R5C13A.Q0 to     R20C21A.A1 u1.dat_l[0]
C1TOFCO_DE  ---     0.786     R20C21A.A1 to    R20C21A.FCO u2/SLICE_355
ROUTE         1     0.000    R20C21A.FCO to    R20C21B.FCI u2/un1_ch1_dat_0_7_cry_0
FCITOFCO_D  ---     0.146    R20C21B.FCI to    R20C21B.FCO u2/SLICE_354
ROUTE         1     0.000    R20C21B.FCO to    R20C21C.FCI u2/un1_ch1_dat_0_7_cry_2
FCITOFCO_D  ---     0.146    R20C21C.FCI to    R20C21C.FCO u2/SLICE_353
ROUTE         1     0.000    R20C21C.FCO to    R20C21D.FCI u2/un1_ch1_dat_0_7_cry_4
FCITOFCO_D  ---     0.146    R20C21D.FCI to    R20C21D.FCO u2/SLICE_352
ROUTE         1     0.000    R20C21D.FCO to    R20C22A.FCI u2/un1_ch1_dat_0_7_cry_6
FCITOFCO_D  ---     0.146    R20C22A.FCI to    R20C22A.FCO u2/SLICE_351
ROUTE         1     0.000    R20C22A.FCO to    R20C22B.FCI u2/un1_ch1_dat_0_7_cry_8
FCITOFCO_D  ---     0.146    R20C22B.FCI to    R20C22B.FCO u2/SLICE_350
ROUTE         1     0.000    R20C22B.FCO to    R20C22C.FCI u2/un1_ch1_dat_0_7_cry_10
FCITOF0_DE  ---     0.517    R20C22C.FCI to     R20C22C.F0 u2/SLICE_349
ROUTE         1     1.602     R20C22C.F0 to     R19C23C.A0 u2/un1_ch1_dat_0_7_0[19]
C0TOFCO_DE  ---     0.905     R19C23C.A0 to    R19C23C.FCO u2/SLICE_326
ROUTE         1     0.000    R19C23C.FCO to    R19C23D.FCI u2/un1_ch1_dat_0_4_cry_20
FCITOFCO_D  ---     0.146    R19C23D.FCI to    R19C23D.FCO u2/SLICE_325
ROUTE         1     0.000    R19C23D.FCO to    R19C24A.FCI u2/un1_ch1_dat_0_4_cry_22
FCITOFCO_D  ---     0.146    R19C24A.FCI to    R19C24A.FCO u2/SLICE_324
ROUTE         1     0.000    R19C24A.FCO to    R19C24B.FCI u2/un1_ch1_dat_0_4_cry_24
FCITOF1_DE  ---     0.569    R19C24B.FCI to     R19C24B.F1 u2/SLICE_323
ROUTE         1     0.000     R19C24B.F1 to    R19C24B.DI1 u2/un1_ch1_dat_0_4_0[26] (to u1.clk_400khz)
                  --------
                   12.559   (33.5% logic, 66.5% route), 12 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1213:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to     R5C13A.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to    R19C24B.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.395ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_l[0]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/ch1_dat_pipe_78  (to u1.clk_400khz +)

   Delay:              12.538ns  (33.1% logic, 66.9% route), 12 logic levels.

 Constraint Details:

     12.538ns physical path delay u1/SLICE_1213 to u2/SLICE_323 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.395ns

 Physical Path Details:

      Data path u1/SLICE_1213 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R5C13A.CLK to      R5C13A.Q0 u1/SLICE_1213 (from u1.clk_400khz)
ROUTE        53     6.749      R5C13A.Q0 to     R20C21A.A1 u1.dat_l[0]
C1TOFCO_DE  ---     0.786     R20C21A.A1 to    R20C21A.FCO u2/SLICE_355
ROUTE         1     0.000    R20C21A.FCO to    R20C21B.FCI u2/un1_ch1_dat_0_7_cry_0
FCITOFCO_D  ---     0.146    R20C21B.FCI to    R20C21B.FCO u2/SLICE_354
ROUTE         1     0.000    R20C21B.FCO to    R20C21C.FCI u2/un1_ch1_dat_0_7_cry_2
FCITOFCO_D  ---     0.146    R20C21C.FCI to    R20C21C.FCO u2/SLICE_353
ROUTE         1     0.000    R20C21C.FCO to    R20C21D.FCI u2/un1_ch1_dat_0_7_cry_4
FCITOF0_DE  ---     0.517    R20C21D.FCI to     R20C21D.F0 u2/SLICE_352
ROUTE         1     1.633     R20C21D.F0 to     R19C22D.B0 u2/un1_ch1_dat_0_7_0[13]
C0TOFCO_DE  ---     0.905     R19C22D.B0 to    R19C22D.FCO u2/SLICE_329
ROUTE         1     0.000    R19C22D.FCO to    R19C23A.FCI u2/un1_ch1_dat_0_4_cry_14
FCITOFCO_D  ---     0.146    R19C23A.FCI to    R19C23A.FCO u2/SLICE_328
ROUTE         1     0.000    R19C23A.FCO to    R19C23B.FCI u2/un1_ch1_dat_0_4_cry_16
FCITOFCO_D  ---     0.146    R19C23B.FCI to    R19C23B.FCO u2/SLICE_327
ROUTE         1     0.000    R19C23B.FCO to    R19C23C.FCI u2/un1_ch1_dat_0_4_cry_18
FCITOFCO_D  ---     0.146    R19C23C.FCI to    R19C23C.FCO u2/SLICE_326
ROUTE         1     0.000    R19C23C.FCO to    R19C23D.FCI u2/un1_ch1_dat_0_4_cry_20
FCITOFCO_D  ---     0.146    R19C23D.FCI to    R19C23D.FCO u2/SLICE_325
ROUTE         1     0.000    R19C23D.FCO to    R19C24A.FCI u2/un1_ch1_dat_0_4_cry_22
FCITOFCO_D  ---     0.146    R19C24A.FCI to    R19C24A.FCO u2/SLICE_324
ROUTE         1     0.000    R19C24A.FCO to    R19C24B.FCI u2/un1_ch1_dat_0_4_cry_24
FCITOF0_DE  ---     0.517    R19C24B.FCI to     R19C24B.F0 u2/SLICE_323
ROUTE         1     0.000     R19C24B.F0 to    R19C24B.DI0 u2/un1_ch1_dat_0_4_0[25] (to u1.clk_400khz)
                  --------
                   12.538   (33.1% logic, 66.9% route), 12 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1213:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to     R5C13A.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to    R19C24B.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.395ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_delay[6]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/cnt_delay[22]  (to u1.clk_400khz +)

   Delay:              12.538ns  (49.2% logic, 50.8% route), 23 logic levels.

 Constraint Details:

     12.538ns physical path delay u1/SLICE_531 to u1/SLICE_523 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.395ns

 Physical Path Details:

      Data path u1/SLICE_531 to u1/SLICE_523:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409      R3C2D.CLK to       R3C2D.Q1 u1/SLICE_531 (from u1.clk_400khz)
ROUTE         2     1.331       R3C2D.Q1 to       R4C3A.A1 u1/cnt_delay[6]
C1TOFCO_DE  ---     0.786       R4C3A.A1 to      R4C3A.FCO u1/SLICE_515
ROUTE         1     0.000      R4C3A.FCO to      R4C3B.FCI u1/un1_cnt_delay_cry_6
FCITOFCO_D  ---     0.146      R4C3B.FCI to      R4C3B.FCO u1/SLICE_514
ROUTE         1     0.000      R4C3B.FCO to      R4C3C.FCI u1/un1_cnt_delay_cry_8
FCITOFCO_D  ---     0.146      R4C3C.FCI to      R4C3C.FCO u1/SLICE_513
ROUTE         1     0.000      R4C3C.FCO to      R4C3D.FCI u1/un1_cnt_delay_cry_10
FCITOFCO_D  ---     0.146      R4C3D.FCI to      R4C3D.FCO u1/SLICE_512
ROUTE         1     0.000      R4C3D.FCO to      R4C4A.FCI u1/un1_cnt_delay_cry_12
FCITOFCO_D  ---     0.146      R4C4A.FCI to      R4C4A.FCO u1/SLICE_511
ROUTE         1     0.000      R4C4A.FCO to      R4C4B.FCI u1/un1_cnt_delay_cry_14
FCITOFCO_D  ---     0.146      R4C4B.FCI to      R4C4B.FCO u1/SLICE_510
ROUTE         1     0.000      R4C4B.FCO to      R4C4C.FCI u1/un1_cnt_delay_cry_16
FCITOFCO_D  ---     0.146      R4C4C.FCI to      R4C4C.FCO u1/SLICE_509
ROUTE         1     0.000      R4C4C.FCO to      R4C4D.FCI u1/un1_cnt_delay_cry_18
FCITOFCO_D  ---     0.146      R4C4D.FCI to      R4C4D.FCO u1/SLICE_508
ROUTE         1     0.000      R4C4D.FCO to      R4C5A.FCI u1/un1_cnt_delay_cry_20
FCITOFCO_D  ---     0.146      R4C5A.FCI to      R4C5A.FCO u1/SLICE_507
ROUTE         1     0.000      R4C5A.FCO to      R4C5B.FCI u1/un1_cnt_delay_cry_22
FCITOF1_DE  ---     0.569      R4C5B.FCI to       R4C5B.F1 u1/SLICE_506
ROUTE         3     2.343       R4C5B.F1 to      R9C15D.C1 u1/un1_cnt_delay_cry_23
CTOF_DEL    ---     0.452      R9C15D.C1 to      R9C15D.F1 u1/SLICE_1344
ROUTE        25     2.692      R9C15D.F1 to       R3C2B.B0 u1/N_440
C0TOFCO_DE  ---     0.905       R3C2B.B0 to      R3C2B.FCO u1/SLICE_533
ROUTE         1     0.000      R3C2B.FCO to      R3C2C.FCI u1/cnt_delay_cry[2]
FCITOFCO_D  ---     0.146      R3C2C.FCI to      R3C2C.FCO u1/SLICE_532
ROUTE         1     0.000      R3C2C.FCO to      R3C2D.FCI u1/cnt_delay_cry[4]
FCITOFCO_D  ---     0.146      R3C2D.FCI to      R3C2D.FCO u1/SLICE_531
ROUTE         1     0.000      R3C2D.FCO to      R3C3A.FCI u1/cnt_delay_cry[6]
FCITOFCO_D  ---     0.146      R3C3A.FCI to      R3C3A.FCO u1/SLICE_530
ROUTE         1     0.000      R3C3A.FCO to      R3C3B.FCI u1/cnt_delay_cry[8]
FCITOFCO_D  ---     0.146      R3C3B.FCI to      R3C3B.FCO u1/SLICE_529
ROUTE         1     0.000      R3C3B.FCO to      R3C3C.FCI u1/cnt_delay_cry[10]
FCITOFCO_D  ---     0.146      R3C3C.FCI to      R3C3C.FCO u1/SLICE_528
ROUTE         1     0.000      R3C3C.FCO to      R3C3D.FCI u1/cnt_delay_cry[12]
FCITOFCO_D  ---     0.146      R3C3D.FCI to      R3C3D.FCO u1/SLICE_527
ROUTE         1     0.000      R3C3D.FCO to      R3C4A.FCI u1/cnt_delay_cry[14]
FCITOFCO_D  ---     0.146      R3C4A.FCI to      R3C4A.FCO u1/SLICE_526
ROUTE         1     0.000      R3C4A.FCO to      R3C4B.FCI u1/cnt_delay_cry[16]
FCITOFCO_D  ---     0.146      R3C4B.FCI to      R3C4B.FCO u1/SLICE_525
ROUTE         1     0.000      R3C4B.FCO to      R3C4C.FCI u1/cnt_delay_cry[18]
FCITOFCO_D  ---     0.146      R3C4C.FCI to      R3C4C.FCO u1/SLICE_524
ROUTE         1     0.000      R3C4C.FCO to      R3C4D.FCI u1/cnt_delay_cry[20]
FCITOF1_DE  ---     0.569      R3C4D.FCI to       R3C4D.F1 u1/SLICE_523
ROUTE         1     0.000       R3C4D.F1 to      R3C4D.DI1 u1/cnt_delay_s[22] (to u1.clk_400khz)
                  --------
                   12.538   (49.2% logic, 50.8% route), 23 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_531:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to      R3C2D.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_523:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to      R3C4D.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.384ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_l[0]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/ch1_dat_pipe_78  (to u1.clk_400khz +)

   Delay:              12.527ns  (33.2% logic, 66.8% route), 12 logic levels.

 Constraint Details:

     12.527ns physical path delay u1/SLICE_1213 to u2/SLICE_323 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.384ns

 Physical Path Details:

      Data path u1/SLICE_1213 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R5C13A.CLK to      R5C13A.Q0 u1/SLICE_1213 (from u1.clk_400khz)
ROUTE        53     6.749      R5C13A.Q0 to     R20C21A.A1 u1.dat_l[0]
C1TOFCO_DE  ---     0.786     R20C21A.A1 to    R20C21A.FCO u2/SLICE_355
ROUTE         1     0.000    R20C21A.FCO to    R20C21B.FCI u2/un1_ch1_dat_0_7_cry_0
FCITOFCO_D  ---     0.146    R20C21B.FCI to    R20C21B.FCO u2/SLICE_354
ROUTE         1     0.000    R20C21B.FCO to    R20C21C.FCI u2/un1_ch1_dat_0_7_cry_2
FCITOFCO_D  ---     0.146    R20C21C.FCI to    R20C21C.FCO u2/SLICE_353
ROUTE         1     0.000    R20C21C.FCO to    R20C21D.FCI u2/un1_ch1_dat_0_7_cry_4
FCITOFCO_D  ---     0.146    R20C21D.FCI to    R20C21D.FCO u2/SLICE_352
ROUTE         1     0.000    R20C21D.FCO to    R20C22A.FCI u2/un1_ch1_dat_0_7_cry_6
FCITOFCO_D  ---     0.146    R20C22A.FCI to    R20C22A.FCO u2/SLICE_351
ROUTE         1     0.000    R20C22A.FCO to    R20C22B.FCI u2/un1_ch1_dat_0_7_cry_8
FCITOFCO_D  ---     0.146    R20C22B.FCI to    R20C22B.FCO u2/SLICE_350
ROUTE         1     0.000    R20C22B.FCO to    R20C22C.FCI u2/un1_ch1_dat_0_7_cry_10
FCITOFCO_D  ---     0.146    R20C22C.FCI to    R20C22C.FCO u2/SLICE_349
ROUTE         1     0.000    R20C22C.FCO to    R20C22D.FCI u2/un1_ch1_dat_0_7_cry_12
FCITOF0_DE  ---     0.517    R20C22D.FCI to     R20C22D.F0 u2/SLICE_348
ROUTE         1     1.622     R20C22D.F0 to     R19C23D.B0 u2/un1_ch1_dat_0_7_0[21]
C0TOFCO_DE  ---     0.905     R19C23D.B0 to    R19C23D.FCO u2/SLICE_325
ROUTE         1     0.000    R19C23D.FCO to    R19C24A.FCI u2/un1_ch1_dat_0_4_cry_22
FCITOFCO_D  ---     0.146    R19C24A.FCI to    R19C24A.FCO u2/SLICE_324
ROUTE         1     0.000    R19C24A.FCO to    R19C24B.FCI u2/un1_ch1_dat_0_4_cry_24
FCITOF0_DE  ---     0.517    R19C24B.FCI to     R19C24B.F0 u2/SLICE_323
ROUTE         1     0.000     R19C24B.F0 to    R19C24B.DI0 u2/un1_ch1_dat_0_4_0[25] (to u1.clk_400khz)
                  --------
                   12.527   (33.2% logic, 66.8% route), 12 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1213:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to     R5C13A.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to    R19C24B.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 6.380ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_l[0]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/ch1_dat_pipe_79  (to u1.clk_400khz +)

   Delay:              12.523ns  (33.1% logic, 66.9% route), 12 logic levels.

 Constraint Details:

     12.523ns physical path delay u1/SLICE_1213 to u2/SLICE_323 exceeds
      6.293ns delay constraint less
      0.000ns skew and
      0.150ns DIN_SET requirement (totaling 6.143ns) by 6.380ns

 Physical Path Details:

      Data path u1/SLICE_1213 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R5C13A.CLK to      R5C13A.Q0 u1/SLICE_1213 (from u1.clk_400khz)
ROUTE        53     6.749      R5C13A.Q0 to     R20C21A.A1 u1.dat_l[0]
C1TOFCO_DE  ---     0.786     R20C21A.A1 to    R20C21A.FCO u2/SLICE_355
ROUTE         1     0.000    R20C21A.FCO to    R20C21B.FCI u2/un1_ch1_dat_0_7_cry_0
FCITOFCO_D  ---     0.146    R20C21B.FCI to    R20C21B.FCO u2/SLICE_354
ROUTE         1     0.000    R20C21B.FCO to    R20C21C.FCI u2/un1_ch1_dat_0_7_cry_2
FCITOFCO_D  ---     0.146    R20C21C.FCI to    R20C21C.FCO u2/SLICE_353
ROUTE         1     0.000    R20C21C.FCO to    R20C21D.FCI u2/un1_ch1_dat_0_7_cry_4
FCITOFCO_D  ---     0.146    R20C21D.FCI to    R20C21D.FCO u2/SLICE_352
ROUTE         1     0.000    R20C21D.FCO to    R20C22A.FCI u2/un1_ch1_dat_0_7_cry_6
FCITOFCO_D  ---     0.146    R20C22A.FCI to    R20C22A.FCO u2/SLICE_351
ROUTE         1     0.000    R20C22A.FCO to    R20C22B.FCI u2/un1_ch1_dat_0_7_cry_8
FCITOFCO_D  ---     0.146    R20C22B.FCI to    R20C22B.FCO u2/SLICE_350
ROUTE         1     0.000    R20C22B.FCO to    R20C22C.FCI u2/un1_ch1_dat_0_7_cry_10
FCITOFCO_D  ---     0.146    R20C22C.FCI to    R20C22C.FCO u2/SLICE_349
ROUTE         1     0.000    R20C22C.FCO to    R20C22D.FCI u2/un1_ch1_dat_0_7_cry_12
FCITOF1_DE  ---     0.569    R20C22D.FCI to     R20C22D.F1 u2/SLICE_348
ROUTE         1     1.633     R20C22D.F1 to     R19C23D.B1 u2/un1_ch1_dat_0_7_0[22]
C1TOFCO_DE  ---     0.786     R19C23D.B1 to    R19C23D.FCO u2/SLICE_325
ROUTE         1     0.000    R19C23D.FCO to    R19C24A.FCI u2/un1_ch1_dat_0_4_cry_22
FCITOFCO_D  ---     0.146    R19C24A.FCI to    R19C24A.FCO u2/SLICE_324
ROUTE         1     0.000    R19C24A.FCO to    R19C24B.FCI u2/un1_ch1_dat_0_4_cry_24
FCITOF1_DE  ---     0.569    R19C24B.FCI to     R19C24B.F1 u2/SLICE_323
ROUTE         1     0.000     R19C24B.F1 to    R19C24B.DI1 u2/un1_ch1_dat_0_4_0[26] (to u1.clk_400khz)
                  --------
                   12.523   (33.1% logic, 66.9% route), 12 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1213:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to     R5C13A.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u2/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     2.660      R2C16C.Q0 to    R19C24B.CLK u1.clk_400khz
                  --------
                    2.660   (0.0% logic, 100.0% route), 0 logic levels.

Warning:  78.070MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "dat_valid" 374.813000 MHz ;
            313 items scored, 289 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 5.446ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat1[12]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[9]  (to dat_valid +)

   Delay:               7.865ns  (33.9% logic, 66.1% route), 5 logic levels.

 Constraint Details:

      7.865ns physical path delay SLICE_653 to u2/SLICE_1159 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.446ns

 Physical Path Details:

      Data path SLICE_653 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C29C.CLK to      R3C29C.Q0 SLICE_653 (from dat_valid)
ROUTE         1     2.558      R3C29C.Q0 to     R10C20C.A1 u2/prox_dat1[12]
C1TOFCO_DE  ---     0.786     R10C20C.A1 to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17D.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.865   (33.9% logic, 66.1% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to SLICE_653:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R3C29C.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17D.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.446ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat1[12]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[11]  (to dat_valid +)
                   FF                        u2/prox_dat2[10]

   Delay:               7.865ns  (33.9% logic, 66.1% route), 5 logic levels.

 Constraint Details:

      7.865ns physical path delay SLICE_653 to u2/SLICE_1165 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.446ns

 Physical Path Details:

      Data path SLICE_653 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R3C29C.CLK to      R3C29C.Q0 SLICE_653 (from dat_valid)
ROUTE         1     2.558      R3C29C.Q0 to     R10C20C.A1 u2/prox_dat1[12]
C1TOFCO_DE  ---     0.786     R10C20C.A1 to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17A.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.865   (33.9% logic, 66.1% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to SLICE_653:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R3C29C.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17A.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.406ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat0[1]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[9]  (to dat_valid +)

   Delay:               7.825ns  (44.9% logic, 55.1% route), 10 logic levels.

 Constraint Details:

      7.825ns physical path delay u2/SLICE_941 to u2/SLICE_1159 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.406ns

 Physical Path Details:

      Data path u2/SLICE_941 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R9C16C.CLK to      R9C16C.Q1 u2/SLICE_941 (from dat_valid)
ROUTE         2     1.669      R9C16C.Q1 to     R10C19B.B0 u2/prox_dat0[1]
C0TOFCO_DE  ---     0.905     R10C19B.B0 to    R10C19B.FCO u2/SLICE_489
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI u2/un1_prox_dat0_1_cry_2
FCITOFCO_D  ---     0.146    R10C19C.FCI to    R10C19C.FCO u2/SLICE_488
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI u2/un1_prox_dat0_1_cry_4
FCITOFCO_D  ---     0.146    R10C19D.FCI to    R10C19D.FCO u2/SLICE_487
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI u2/un1_prox_dat0_1_cry_6
FCITOFCO_D  ---     0.146    R10C20A.FCI to    R10C20A.FCO u2/SLICE_486
ROUTE         1     0.000    R10C20A.FCO to    R10C20B.FCI u2/un1_prox_dat0_1_cry_8
FCITOFCO_D  ---     0.146    R10C20B.FCI to    R10C20B.FCO u2/SLICE_485
ROUTE         1     0.000    R10C20B.FCO to    R10C20C.FCI u2/un1_prox_dat0_1_cry_10
FCITOFCO_D  ---     0.146    R10C20C.FCI to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17D.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.825   (44.9% logic, 55.1% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to u2/SLICE_941:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R9C16C.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17D.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.406ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat0[1]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[11]  (to dat_valid +)
                   FF                        u2/prox_dat2[10]

   Delay:               7.825ns  (44.9% logic, 55.1% route), 10 logic levels.

 Constraint Details:

      7.825ns physical path delay u2/SLICE_941 to u2/SLICE_1165 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.406ns

 Physical Path Details:

      Data path u2/SLICE_941 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R9C16C.CLK to      R9C16C.Q1 u2/SLICE_941 (from dat_valid)
ROUTE         2     1.669      R9C16C.Q1 to     R10C19B.B0 u2/prox_dat0[1]
C0TOFCO_DE  ---     0.905     R10C19B.B0 to    R10C19B.FCO u2/SLICE_489
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI u2/un1_prox_dat0_1_cry_2
FCITOFCO_D  ---     0.146    R10C19C.FCI to    R10C19C.FCO u2/SLICE_488
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI u2/un1_prox_dat0_1_cry_4
FCITOFCO_D  ---     0.146    R10C19D.FCI to    R10C19D.FCO u2/SLICE_487
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI u2/un1_prox_dat0_1_cry_6
FCITOFCO_D  ---     0.146    R10C20A.FCI to    R10C20A.FCO u2/SLICE_486
ROUTE         1     0.000    R10C20A.FCO to    R10C20B.FCI u2/un1_prox_dat0_1_cry_8
FCITOFCO_D  ---     0.146    R10C20B.FCI to    R10C20B.FCO u2/SLICE_485
ROUTE         1     0.000    R10C20B.FCO to    R10C20C.FCI u2/un1_prox_dat0_1_cry_10
FCITOFCO_D  ---     0.146    R10C20C.FCI to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17A.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.825   (44.9% logic, 55.1% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to u2/SLICE_941:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R9C16C.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17A.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.402ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat0[0]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[9]  (to dat_valid +)

   Delay:               7.821ns  (45.3% logic, 54.7% route), 11 logic levels.

 Constraint Details:

      7.821ns physical path delay u2/SLICE_941 to u2/SLICE_1159 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.402ns

 Physical Path Details:

      Data path u2/SLICE_941 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R9C16C.CLK to      R9C16C.Q0 u2/SLICE_941 (from dat_valid)
ROUTE         2     1.638      R9C16C.Q0 to     R10C19A.A1 u2/prox_dat0[0]
C1TOFCO_DE  ---     0.786     R10C19A.A1 to    R10C19A.FCO u2/SLICE_490
ROUTE         1     0.000    R10C19A.FCO to    R10C19B.FCI u2/un1_prox_dat0_1_cry_0
FCITOFCO_D  ---     0.146    R10C19B.FCI to    R10C19B.FCO u2/SLICE_489
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI u2/un1_prox_dat0_1_cry_2
FCITOFCO_D  ---     0.146    R10C19C.FCI to    R10C19C.FCO u2/SLICE_488
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI u2/un1_prox_dat0_1_cry_4
FCITOFCO_D  ---     0.146    R10C19D.FCI to    R10C19D.FCO u2/SLICE_487
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI u2/un1_prox_dat0_1_cry_6
FCITOFCO_D  ---     0.146    R10C20A.FCI to    R10C20A.FCO u2/SLICE_486
ROUTE         1     0.000    R10C20A.FCO to    R10C20B.FCI u2/un1_prox_dat0_1_cry_8
FCITOFCO_D  ---     0.146    R10C20B.FCI to    R10C20B.FCO u2/SLICE_485
ROUTE         1     0.000    R10C20B.FCO to    R10C20C.FCI u2/un1_prox_dat0_1_cry_10
FCITOFCO_D  ---     0.146    R10C20C.FCI to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17D.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.821   (45.3% logic, 54.7% route), 11 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to u2/SLICE_941:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R9C16C.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17D.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.402ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat0[0]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[11]  (to dat_valid +)
                   FF                        u2/prox_dat2[10]

   Delay:               7.821ns  (45.3% logic, 54.7% route), 11 logic levels.

 Constraint Details:

      7.821ns physical path delay u2/SLICE_941 to u2/SLICE_1165 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.402ns

 Physical Path Details:

      Data path u2/SLICE_941 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R9C16C.CLK to      R9C16C.Q0 u2/SLICE_941 (from dat_valid)
ROUTE         2     1.638      R9C16C.Q0 to     R10C19A.A1 u2/prox_dat0[0]
C1TOFCO_DE  ---     0.786     R10C19A.A1 to    R10C19A.FCO u2/SLICE_490
ROUTE         1     0.000    R10C19A.FCO to    R10C19B.FCI u2/un1_prox_dat0_1_cry_0
FCITOFCO_D  ---     0.146    R10C19B.FCI to    R10C19B.FCO u2/SLICE_489
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI u2/un1_prox_dat0_1_cry_2
FCITOFCO_D  ---     0.146    R10C19C.FCI to    R10C19C.FCO u2/SLICE_488
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI u2/un1_prox_dat0_1_cry_4
FCITOFCO_D  ---     0.146    R10C19D.FCI to    R10C19D.FCO u2/SLICE_487
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI u2/un1_prox_dat0_1_cry_6
FCITOFCO_D  ---     0.146    R10C20A.FCI to    R10C20A.FCO u2/SLICE_486
ROUTE         1     0.000    R10C20A.FCO to    R10C20B.FCI u2/un1_prox_dat0_1_cry_8
FCITOFCO_D  ---     0.146    R10C20B.FCI to    R10C20B.FCO u2/SLICE_485
ROUTE         1     0.000    R10C20B.FCO to    R10C20C.FCI u2/un1_prox_dat0_1_cry_10
FCITOFCO_D  ---     0.146    R10C20C.FCI to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17A.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.821   (45.3% logic, 54.7% route), 11 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to u2/SLICE_941:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R9C16C.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17A.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.400ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat1[5]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[9]  (to dat_valid +)

   Delay:               7.819ns  (41.2% logic, 58.8% route), 8 logic levels.

 Constraint Details:

      7.819ns physical path delay u2/SLICE_649 to u2/SLICE_1159 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.400ns

 Physical Path Details:

      Data path u2/SLICE_649 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409    R12C18D.CLK to     R12C18D.Q1 u2/SLICE_649 (from dat_valid)
ROUTE         1     1.955     R12C18D.Q1 to     R10C19D.A0 u2/prox_dat1[5]
C0TOFCO_DE  ---     0.905     R10C19D.A0 to    R10C19D.FCO u2/SLICE_487
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI u2/un1_prox_dat0_1_cry_6
FCITOFCO_D  ---     0.146    R10C20A.FCI to    R10C20A.FCO u2/SLICE_486
ROUTE         1     0.000    R10C20A.FCO to    R10C20B.FCI u2/un1_prox_dat0_1_cry_8
FCITOFCO_D  ---     0.146    R10C20B.FCI to    R10C20B.FCO u2/SLICE_485
ROUTE         1     0.000    R10C20B.FCO to    R10C20C.FCI u2/un1_prox_dat0_1_cry_10
FCITOFCO_D  ---     0.146    R10C20C.FCI to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17D.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.819   (41.2% logic, 58.8% route), 8 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to u2/SLICE_649:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to    R12C18D.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17D.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.400ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat1[5]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[11]  (to dat_valid +)
                   FF                        u2/prox_dat2[10]

   Delay:               7.819ns  (41.2% logic, 58.8% route), 8 logic levels.

 Constraint Details:

      7.819ns physical path delay u2/SLICE_649 to u2/SLICE_1165 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.400ns

 Physical Path Details:

      Data path u2/SLICE_649 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409    R12C18D.CLK to     R12C18D.Q1 u2/SLICE_649 (from dat_valid)
ROUTE         1     1.955     R12C18D.Q1 to     R10C19D.A0 u2/prox_dat1[5]
C0TOFCO_DE  ---     0.905     R10C19D.A0 to    R10C19D.FCO u2/SLICE_487
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI u2/un1_prox_dat0_1_cry_6
FCITOFCO_D  ---     0.146    R10C20A.FCI to    R10C20A.FCO u2/SLICE_486
ROUTE         1     0.000    R10C20A.FCO to    R10C20B.FCI u2/un1_prox_dat0_1_cry_8
FCITOFCO_D  ---     0.146    R10C20B.FCI to    R10C20B.FCO u2/SLICE_485
ROUTE         1     0.000    R10C20B.FCO to    R10C20C.FCI u2/un1_prox_dat0_1_cry_10
FCITOFCO_D  ---     0.146    R10C20C.FCI to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17A.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.819   (41.2% logic, 58.8% route), 8 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to u2/SLICE_649:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to    R12C18D.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17A.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.273ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat1[10]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[11]  (to dat_valid +)
                   FF                        u2/prox_dat2[10]

   Delay:               7.692ns  (36.6% logic, 63.4% route), 6 logic levels.

 Constraint Details:

      7.692ns physical path delay SLICE_652 to u2/SLICE_1165 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.273ns

 Physical Path Details:

      Data path SLICE_652 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R5C29A.CLK to      R5C29A.Q0 SLICE_652 (from dat_valid)
ROUTE         1     2.239      R5C29A.Q0 to     R10C20B.B1 u2/prox_dat1[10]
C1TOFCO_DE  ---     0.786     R10C20B.B1 to    R10C20B.FCO u2/SLICE_485
ROUTE         1     0.000    R10C20B.FCO to    R10C20C.FCI u2/un1_prox_dat0_1_cry_10
FCITOFCO_D  ---     0.146    R10C20C.FCI to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17A.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.692   (36.6% logic, 63.4% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to SLICE_652:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R5C29A.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1165:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17A.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 5.273ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/prox_dat1[10]  (from dat_valid +)
   Destination:    FF         Data in        u2/prox_dat2[9]  (to dat_valid +)

   Delay:               7.692ns  (36.6% logic, 63.4% route), 6 logic levels.

 Constraint Details:

      7.692ns physical path delay SLICE_652 to u2/SLICE_1159 exceeds
      2.668ns delay constraint less
      0.000ns skew and
      0.249ns CE_SET requirement (totaling 2.419ns) by 5.273ns

 Physical Path Details:

      Data path SLICE_652 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R5C29A.CLK to      R5C29A.Q0 SLICE_652 (from dat_valid)
ROUTE         1     2.239      R5C29A.Q0 to     R10C20B.B1 u2/prox_dat1[10]
C1TOFCO_DE  ---     0.786     R10C20B.B1 to    R10C20B.FCO u2/SLICE_485
ROUTE         1     0.000    R10C20B.FCO to    R10C20C.FCI u2/un1_prox_dat0_1_cry_10
FCITOFCO_D  ---     0.146    R10C20C.FCI to    R10C20C.FCO u2/SLICE_484
ROUTE         1     0.000    R10C20C.FCO to    R10C20D.FCI u2/un1_prox_dat0_1_cry_12
FCITOF1_DE  ---     0.569    R10C20D.FCI to     R10C20D.F1 u2/SLICE_483
ROUTE         1     0.851     R10C20D.F1 to      R9C20C.A1 u2/un1_prox_dat0_1[14]
CTOF_DEL    ---     0.452      R9C20C.A1 to      R9C20C.F1 u2/SLICE_1170
ROUTE         1     0.384      R9C20C.F1 to      R9C20C.C0 u2/un1_prox_dat0_2lto15_1
CTOF_DEL    ---     0.452      R9C20C.C0 to      R9C20C.F0 u2/SLICE_1170
ROUTE         2     1.404      R9C20C.F0 to      R8C17D.CE u2/un1_prox_dat0_2lto15 (to dat_valid)
                  --------
                    7.692   (36.6% logic, 63.4% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_1196 to SLICE_652:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R5C29A.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_1196 to u2/SLICE_1159:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        18     4.662      R2C16A.Q0 to     R8C17D.CLK dat_valid
                  --------
                    4.662   (0.0% logic, 100.0% route), 0 logic levels.

Warning: 123.244MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "clk_c" 41.487000 MHz ;   |   41.487 MHz|    0.367 MHz|   2 *
                                        |             |             |
FREQUENCY NET "u3.clk_40khz" 39.330000  |             |             |
MHz ;                                   |   39.330 MHz|    0.107 MHz|  57 *
                                        |             |             |
FREQUENCY NET "u1.clk_400khz"           |             |             |
158.907000 MHz ;                        |  158.907 MHz|   78.070 MHz|  25 *
                                        |             |             |
FREQUENCY NET "dat_valid" 374.813000    |             |             |
MHz ;                                   |  374.813 MHz|  123.244 MHz|   5 *
                                        |             |             |
----------------------------------------------------------------------------


4 preferences(marked by "*" above) not met.

----------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
----------------------------------------------------------------------------
u2/u1/CO2_49                            |       3|    8190|     65.12%
                                        |        |        |
u2/u1/CO0_62                            |       7|    8190|     65.12%
                                        |        |        |
u2/u1/shift_reg_218_i_i_a2_0_RNIK9H9MR[3|        |        |
7]                                      |       1|    8190|     65.12%
                                        |        |        |
u2/u1/shift_reg_218[38]                 |       6|    8190|     65.12%
                                        |        |        |
u2/u1/CO0_95                            |      10|    8190|     65.12%
                                        |        |        |
u2/u1/shift_reg_113_0_a2_0_a2_RNIEE9911_|        |        |
0[37]                                   |       1|    8174|     64.99%
                                        |        |        |
u2/u1/CO2_85                            |       7|    8174|     64.99%
                                        |        |        |
u2/u1/shift_reg_110_RNIPJKQR2[34]       |       3|    8174|     64.99%
                                        |        |        |
u2/u1/ANB1_98                           |       5|    8173|     64.98%
                                        |        |        |
u2/u1/un1_shift_reg_4_c3_0_a1_0         |       2|    7917|     62.95%
                                        |        |        |
u2.u1.CO0_11                            |      11|    7917|     62.95%
                                        |        |        |
u2.u1._l30.un1_shift_reg_4              |       3|    7915|     62.93%
                                        |        |        |
u2/u1/shift_reg_365[46]                 |       6|    7914|     62.92%
                                        |        |        |
u2/u1/un1_shift_reg_axb0_3              |       6|    7910|     62.89%
                                        |        |        |
u2/u1/un1_shift_reg_4_c3_0_a1_a0        |       1|    7854|     62.45%
                                        |        |        |
u2/u1/CO2_69                            |       7|    7351|     58.45%
                                        |        |        |
u2/u1/shift_reg_180[38]                 |       5|    7351|     58.45%
                                        |        |        |
u2/u1/SUM1_31_3_1                       |       4|    7278|     57.87%
                                        |        |        |
u2/u1/CO0_40                            |       4|    7276|     57.85%
                                        |        |        |
u2/u1/shift_reg_284[38]                 |       6|    7271|     57.81%
                                        |        |        |
u2/u1/CO0_32                            |       6|    7041|     55.98%
                                        |        |        |
u2/u1/CO2_80                            |       9|    6952|     55.28%
                                        |        |        |
u2/u1/shift_reg_27_a0_RNIN15GG1[34]     |       2|    6920|     55.02%
                                        |        |        |
u2/u1/ANB1_120                          |       3|    6915|     54.98%
                                        |        |        |
u2/u1/shift_reg_27[34]                  |       2|    6915|     54.98%
                                        |        |        |
u2/u1/shift_reg_0_2[34]                 |       1|    6913|     54.97%
                                        |        |        |
u2/u1/shift_reg_0_1[34]                 |       1|    6913|     54.97%
                                        |        |        |
u2/un1_lux_1_s0_m1_0_cry_16             |       1|    6759|     53.74%
                                        |        |        |
u2/un1_lux_1_s0_m1_0_cry_18             |       1|    6759|     53.74%
                                        |        |        |
u2/un1_lux_1_s0_m1_0_cry_20             |       1|    6759|     53.74%
                                        |        |        |
ch1_dat[1]                              |      11|    6757|     53.73%
                                        |        |        |
u2/un1_ch1_dat_1_cry_7                  |       1|    6736|     53.56%
                                        |        |        |
u2/u1/CO0_68                            |       7|    6629|     52.71%
                                        |        |        |
u2/un1_lux_1_s0_m1_0_cry_14             |       1|    6318|     50.23%
                                        |        |        |
u2/u1/CO1_46                            |       2|    6253|     49.72%
                                        |        |        |
u2/u1/ANB1_103                          |       4|    6000|     47.71%
                                        |        |        |
u2/u1/CO1_103                           |       3|    5992|     47.64%
                                        |        |        |
u2/u1/shift_reg_180cf1_N_2L1_0          |       1|    5969|     47.46%
                                        |        |        |
u2/un1_ch1_dat_1_cry_9                  |       1|    5941|     47.24%
                                        |        |        |
u2/u1/un1_shift_reg_c3_d                |       1|    5597|     44.50%
                                        |        |        |
u2/un1_lux_1_s0_m1_0_cry_22             |       1|    5575|     44.33%
                                        |        |        |
u2/un1_lux_1_s0_m1_0_cry_23_0_S1        |       1|    5542|     44.06%
                                        |        |        |
u2/un1_lux_1_s0_m1[26]                  |       3|    5542|     44.06%
                                        |        |        |
u2/u1/shift_reg_61[33]                  |       4|    5266|     41.87%
                                        |        |        |
u2.u1.shift_reg_452[50]                 |       9|    4949|     39.35%
                                        |        |        |
u2/un1_lux_1_s0_m1_0_cry_12             |       1|    4448|     35.37%
                                        |        |        |
u2.u1._l31.shift_reg_480_c3             |       2|    4406|     35.03%
                                        |        |        |
u2/u1/shift_reg_51[33]                  |       4|    4308|     34.25%
                                        |        |        |
u2/u1/ANB1_107                          |       4|    4293|     34.13%
                                        |        |        |
u2/u1/CO2_111                           |       1|    4226|     33.60%
                                        |        |        |
led_reg6_i                              |       1|    4094|     32.55%
                                        |        |        |
lux_data[16]                            |      11|    4094|     32.55%
                                        |        |        |
u2/u1/CO2_117_sx_0                      |       1|    3945|     31.37%
                                        |        |        |
u2/u1/ANB1_114                          |       4|    3821|     30.38%
                                        |        |        |
u1/un1_cnt_delay_cry_23                 |       3|    3764|     29.93%
                                        |        |        |
u1/N_440                                |      25|    3764|     29.93%
                                        |        |        |
u1/un1_cnt_delay_cry_22                 |       1|    3760|     29.90%
                                        |        |        |
u1/un1_cnt_delay_cry_20                 |       1|    3433|     27.30%
                                        |        |        |
u2/un1_ch1_dat_1[11]                    |       3|    3350|     26.64%
                                        |        |        |
u2/un1_lux_1_d1_58_0                    |       1|    3223|     25.63%
                                        |        |        |
u1/un1_cnt_delay_cry_18                 |       1|    3192|     25.38%
                                        |        |        |
u3/data_12_7_am_RNO_0[13]               |       1|    3178|     25.27%
                                        |        |        |
u3/data_12_7_am_RNO[13]                 |       1|    3178|     25.27%
                                        |        |        |
u3/data_12[13]                          |       1|    3178|     25.27%
                                        |        |        |
u2.u1._l31.shift_reg_480[48]            |      11|    3025|     24.05%
                                        |        |        |
u3/N_12_0                               |       2|    3010|     23.93%
                                        |        |        |
u2/u1/shift_reg_41[33]                  |       2|    2970|     23.61%
                                        |        |        |
u1/un1_cnt_delay_cry_16                 |       1|    2887|     22.95%
                                        |        |        |
u2/u1/shift_reg_61[34]                  |       4|    2671|     21.24%
                                        |        |        |
u1/un1_cnt_delay_cry_14                 |       1|    2515|     20.00%
                                        |        |        |
u1/cnt_delay_cry[12]                    |       1|    2480|     19.72%
                                        |        |        |
u1/cnt_delay_cry[10]                    |       1|    2426|     19.29%
                                        |        |        |
u2/un1_ch1_dat_1_cry_11                 |       1|    2391|     19.01%
                                        |        |        |
u2/u1/shift_reg_365_c1                  |       1|    2317|     18.42%
                                        |        |        |
u1/cnt_delay_cry[14]                    |       1|    2290|     18.21%
                                        |        |        |
u2/u1/shift_reg_71[34]                  |       4|    2267|     18.02%
                                        |        |        |
u1/cnt_delay_cry[8]                     |       1|    2218|     17.64%
                                        |        |        |
u2/u1/CO2_75                            |       8|    2155|     17.13%
                                        |        |        |
u2/u1/CO2_79_sx_0                       |       1|    2150|     17.09%
                                        |        |        |
u1/cnt_delay_cry[6]                     |       1|    1965|     15.62%
                                        |        |        |
u1/cnt_delay_cry[16]                    |       1|    1955|     15.54%
                                        |        |        |
u1/un1_cnt_delay_cry_12                 |       1|    1943|     15.45%
                                        |        |        |
u2/u1/CO0_48                            |       8|    1937|     15.40%
                                        |        |        |
u2.u1.shift_reg_452[51]                 |       7|    1765|     14.03%
                                        |        |        |
u2/u1/shift_reg_71[33]                  |       4|    1630|     12.96%
                                        |        |        |
u1/cnt_delay_cry[4]                     |       1|    1610|     12.80%
                                        |        |        |
u2/u1/shift_reg_84[33]                  |       6|    1586|     12.61%
                                        |        |        |
u2/u1/CO2_67_sx                         |       1|    1561|     12.41%
                                        |        |        |
u2/u1/CO2_63                            |       5|    1561|     12.41%
                                        |        |        |
u1/cnt_delay_cry[18]                    |       1|    1506|     11.97%
                                        |        |        |
u1/un1_cnt_delay_cry_10                 |       1|    1433|     11.39%
                                        |        |        |
u2/un1_lux_1_d3_cry_20                  |       1|    1409|     11.20%
                                        |        |        |
u2/un1_lux_1_d3_cry_22                  |       1|    1409|     11.20%
                                        |        |        |
u2/un1_lux_1_d3_cry_24                  |       1|    1409|     11.20%
                                        |        |        |
ch1_dat[14]                             |      11|    1409|     11.20%
                                        |        |        |
u2/un1_ch1_dat_3_0_cry_12               |       1|    1407|     11.19%
                                        |        |        |
u2/un1_lux_1_s3[26]                     |       3|    1401|     11.14%
                                        |        |        |
u2/u1/shift_reg_27_a0[34]               |       1|    1401|     11.14%
                                        |        |        |
u2/un1_ch1_dat_3_0_cry_14               |       1|    1381|     10.98%
                                        |        |        |
----------------------------------------------------------------------------


Clock Domains Analysis
------------------------

Found 4 clocks:

Clock Domain: u3.clk_40khz   Source: u3/SLICE_667.Q0   Loads: 20
   Covered under: FREQUENCY NET "u3.clk_40khz" 39.330000 MHz ;

   Data transfers from:
   Clock Domain: u1.clk_400khz   Source: u1/SLICE_586.Q0
      Covered under: FREQUENCY NET "u3.clk_40khz" 39.330000 MHz ;   Transfers: 348

Clock Domain: u1.clk_400khz   Source: u1/SLICE_586.Q0   Loads: 258
   Covered under: FREQUENCY NET "u1.clk_400khz" 158.907000 MHz ;

Clock Domain: dat_valid   Source: u1/SLICE_1196.Q0   Loads: 18
   Covered under: FREQUENCY NET "dat_valid" 374.813000 MHz ;

   Data transfers from:
   Clock Domain: u1.clk_400khz   Source: u1/SLICE_586.Q0
      Covered under: FREQUENCY NET "dat_valid" 374.813000 MHz ;   Transfers: 16

Clock Domain: clk_c   Source: clk.PAD   Loads: 59
   Covered under: FREQUENCY NET "clk_c" 41.487000 MHz ;

   Data transfers from:
   Clock Domain: u1.clk_400khz   Source: u1/SLICE_586.Q0
      Covered under: FREQUENCY NET "clk_c" 41.487000 MHz ;   Transfers: 348

   Clock Domain: dat_valid   Source: u1/SLICE_1196.Q0
      Covered under: FREQUENCY NET "clk_c" 41.487000 MHz ;   Transfers: 2


Timing summary (Setup):
---------------

Timing errors: 12577  Score: 4294967295
Cumulative negative slack: 4294967295

Constraints cover 2147483647 paths, 5 nets, and 8749 connections (98.29% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.14.0.75.2
Fri Mar 07 11:30:28 2025

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2024 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o prox_detect_impl1.twr -gui -msgset C:/Users/lumfl/Downloads/NetDisk/V4.0/STEP-MXO2/myTrafficLight/promote.xml prox_detect_impl1.ncd prox_detect_impl1.prf 
Design file:     prox_detect_impl1.ncd
Preference file: prox_detect_impl1.prf
Device,speed:    LCMXO2-4000HC,m
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "clk_c" 41.487000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_400khz[5]  (from clk_c +)
   Destination:    FF         Data in        u1/cnt_400khz[5]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u1/SLICE_518 to u1/SLICE_518 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u1/SLICE_518 to u1/SLICE_518:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R3C15D.CLK to      R3C15D.Q0 u1/SLICE_518 (from clk_c)
ROUTE         2     0.132      R3C15D.Q0 to      R3C15D.A0 u1/cnt_400khz[5]
CTOF_DEL    ---     0.101      R3C15D.A0 to      R3C15D.F0 u1/SLICE_518
ROUTE         1     0.000      R3C15D.F0 to     R3C15D.DI0 u1/un3_cnt_400khz[5] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_518:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R3C15D.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u1/SLICE_518:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R3C15D.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u5/u1/cnt_p[2]  (from clk_c +)
   Destination:    FF         Data in        u5/u1/cnt_p[2]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u5/u1/SLICE_36 to u5/u1/SLICE_36 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u5/u1/SLICE_36 to u5/u1/SLICE_36:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C27B.CLK to      R2C27B.Q1 u5/u1/SLICE_36 (from clk_c)
ROUTE         3     0.132      R2C27B.Q1 to      R2C27B.A1 u5/u1/cnt_p[2]
CTOF_DEL    ---     0.101      R2C27B.A1 to      R2C27B.F1 u5/u1/SLICE_36
ROUTE         1     0.000      R2C27B.F1 to     R2C27B.DI1 u5/u1/un3_cnt_p[2] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u5/u1/SLICE_36:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C27B.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u5/u1/SLICE_36:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C27B.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_400khz[8]  (from clk_c +)
   Destination:    FF         Data in        u1/cnt_400khz[8]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u1/SLICE_517 to u1/SLICE_517 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u1/SLICE_517 to u1/SLICE_517:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R3C16A.CLK to      R3C16A.Q1 u1/SLICE_517 (from clk_c)
ROUTE         2     0.132      R3C16A.Q1 to      R3C16A.A1 u1/cnt_400khz[8]
CTOF_DEL    ---     0.101      R3C16A.A1 to      R3C16A.F1 u1/SLICE_517
ROUTE         1     0.000      R3C16A.F1 to     R3C16A.DI1 u1/un3_cnt_400khz[8] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_517:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R3C16A.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u1/SLICE_517:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R3C16A.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u5/u1/cnt_p[17]  (from clk_c +)
   Destination:    FF         Data in        u5/u1/cnt_p[17]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u5/u1/SLICE_28 to u5/u1/SLICE_28 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u5/u1/SLICE_28 to u5/u1/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C29B.CLK to      R2C29B.Q0 u5/u1/SLICE_28 (from clk_c)
ROUTE         2     0.132      R2C29B.Q0 to      R2C29B.A0 u5/u1/cnt_p[17]
CTOF_DEL    ---     0.101      R2C29B.A0 to      R2C29B.F0 u5/u1/SLICE_28
ROUTE         1     0.000      R2C29B.F0 to     R2C29B.DI0 u5/u1/un3_cnt_p[17] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u5/u1/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C29B.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u5/u1/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C29B.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u5/u1/cnt_p[20]  (from clk_c +)
   Destination:    FF         Data in        u5/u1/cnt_p[20]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u5/u1/SLICE_27 to u5/u1/SLICE_27 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u5/u1/SLICE_27 to u5/u1/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C29C.CLK to      R2C29C.Q1 u5/u1/SLICE_27 (from clk_c)
ROUTE         2     0.132      R2C29C.Q1 to      R2C29C.A1 u5/u1/cnt_p[20]
CTOF_DEL    ---     0.101      R2C29C.A1 to      R2C29C.F1 u5/u1/SLICE_27
ROUTE         1     0.000      R2C29C.F1 to     R2C29C.DI1 u5/u1/un3_cnt_p[20] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u5/u1/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C29C.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u5/u1/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C29C.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u5/u2/cnt_p[5]  (from clk_c +)
   Destination:    FF         Data in        u5/u2/cnt_p[5]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u5/u2/SLICE_15 to u5/u2/SLICE_15 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u5/u2/SLICE_15 to u5/u2/SLICE_15:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R19C27D.CLK to     R19C27D.Q0 u5/u2/SLICE_15 (from clk_c)
ROUTE         2     0.132     R19C27D.Q0 to     R19C27D.A0 u5/u2/cnt_p[5]
CTOF_DEL    ---     0.101     R19C27D.A0 to     R19C27D.F0 u5/u2/SLICE_15
ROUTE         1     0.000     R19C27D.F0 to    R19C27D.DI0 u5/u2/un16_cnt_p[5] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u5/u2/SLICE_15:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to    R19C27D.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u5/u2/SLICE_15:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to    R19C27D.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u5/u1/cnt_p[32]  (from clk_c +)
   Destination:    FF         Data in        u5/u1/cnt_p[32]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u5/u1/SLICE_21 to u5/u1/SLICE_21 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u5/u1/SLICE_21 to u5/u1/SLICE_21:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C31A.CLK to      R2C31A.Q1 u5/u1/SLICE_21 (from clk_c)
ROUTE         2     0.132      R2C31A.Q1 to      R2C31A.A1 u5/u1/cnt_p[32]
CTOF_DEL    ---     0.101      R2C31A.A1 to      R2C31A.F1 u5/u1/SLICE_21
ROUTE         1     0.000      R2C31A.F1 to     R2C31A.DI1 u5/u1/un3_cnt_p[32] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u5/u1/SLICE_21:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C31A.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u5/u1/SLICE_21:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C31A.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u5/u1/cnt_p[27]  (from clk_c +)
   Destination:    FF         Data in        u5/u1/cnt_p[27]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u5/u1/SLICE_23 to u5/u1/SLICE_23 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u5/u1/SLICE_23 to u5/u1/SLICE_23:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C30C.CLK to      R2C30C.Q0 u5/u1/SLICE_23 (from clk_c)
ROUTE         2     0.132      R2C30C.Q0 to      R2C30C.A0 u5/u1/cnt_p[27]
CTOF_DEL    ---     0.101      R2C30C.A0 to      R2C30C.F0 u5/u1/SLICE_23
ROUTE         1     0.000      R2C30C.F0 to     R2C30C.DI0 u5/u1/un3_cnt_p[27] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u5/u1/SLICE_23:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C30C.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u5/u1/SLICE_23:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C30C.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u5/u1/cnt_p[15]  (from clk_c +)
   Destination:    FF         Data in        u5/u1/cnt_p[15]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u5/u1/SLICE_29 to u5/u1/SLICE_29 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u5/u1/SLICE_29 to u5/u1/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C29A.CLK to      R2C29A.Q0 u5/u1/SLICE_29 (from clk_c)
ROUTE         2     0.132      R2C29A.Q0 to      R2C29A.A0 u5/u1/cnt_p[15]
CTOF_DEL    ---     0.101      R2C29A.A0 to      R2C29A.F0 u5/u1/SLICE_29
ROUTE         1     0.000      R2C29A.F0 to     R2C29A.DI0 u5/u1/un3_cnt_p[15] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u5/u1/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C29A.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u5/u1/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to     R2C29A.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u5/u2/cnt_p[1]  (from clk_c +)
   Destination:    FF         Data in        u5/u2/cnt_p[1]  (to clk_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u5/u2/SLICE_17 to u5/u2/SLICE_17 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u5/u2/SLICE_17 to u5/u2/SLICE_17:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R19C27B.CLK to     R19C27B.Q0 u5/u2/SLICE_17 (from clk_c)
ROUTE         2     0.132     R19C27B.Q0 to     R19C27B.A0 u5/u2/cnt_p[1]
CTOF_DEL    ---     0.101     R19C27B.A0 to     R19C27B.F0 u5/u2/SLICE_17
ROUTE         1     0.000     R19C27B.F0 to    R19C27B.DI0 u5/u2/un16_cnt_p[1] (to clk_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u5/u2/SLICE_17:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to    R19C27B.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk to u5/u2/SLICE_17:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        59     1.116       C1.PADDI to    R19C27B.CLK clk_c
                  --------
                    1.116   (0.0% logic, 100.0% route), 0 logic levels.


================================================================================
Preference: FREQUENCY NET "u3.clk_40khz" 39.330000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.379ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_write[3]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/cnt_write[3]  (to u3.clk_40khz +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay u3/SLICE_44 to u3/SLICE_44 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path u3/SLICE_44 to u3/SLICE_44:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R15C27C.CLK to     R15C27C.Q0 u3/SLICE_44 (from u3.clk_40khz)
ROUTE         3     0.132     R15C27C.Q0 to     R15C27C.A0 u3/cnt_write[3]
CTOF_DEL    ---     0.101     R15C27C.A0 to     R15C27C.F0 u3/SLICE_44
ROUTE         1     0.000     R15C27C.F0 to    R15C27C.DI0 u3/cnt_write_s[3] (to u3.clk_40khz)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_44:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27C.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_44:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27C.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.380ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_write[4]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/cnt_write[4]  (to u3.clk_40khz +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay u3/SLICE_44 to u3/SLICE_44 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path u3/SLICE_44 to u3/SLICE_44:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R15C27C.CLK to     R15C27C.Q1 u3/SLICE_44 (from u3.clk_40khz)
ROUTE         4     0.133     R15C27C.Q1 to     R15C27C.A1 u3/cnt_write[4]
CTOF_DEL    ---     0.101     R15C27C.A1 to     R15C27C.F1 u3/SLICE_44
ROUTE         1     0.000     R15C27C.F1 to    R15C27C.DI1 u3/cnt_write_s[4] (to u3.clk_40khz)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_44:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27C.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_44:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27C.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.380ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_write[2]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/cnt_write[2]  (to u3.clk_40khz +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay u3/SLICE_45 to u3/SLICE_45 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path u3/SLICE_45 to u3/SLICE_45:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R15C27B.CLK to     R15C27B.Q1 u3/SLICE_45 (from u3.clk_40khz)
ROUTE         6     0.133     R15C27B.Q1 to     R15C27B.A1 u3/cnt_write[2]
CTOF_DEL    ---     0.101     R15C27B.A1 to     R15C27B.F1 u3/SLICE_45
ROUTE         1     0.000     R15C27B.F1 to    R15C27B.DI1 u3/cnt_write_s[2] (to u3.clk_40khz)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_45:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_45:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.380ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_main[1]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/cnt_main[1]  (to u3.clk_40khz +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay u3/SLICE_673 to u3/SLICE_673 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path u3/SLICE_673 to u3/SLICE_673:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C27B.CLK to      R9C27B.Q1 u3/SLICE_673 (from u3.clk_40khz)
ROUTE        38     0.133      R9C27B.Q1 to      R9C27B.A1 u3/cnt_main[1]
CTOF_DEL    ---     0.101      R9C27B.A1 to      R9C27B.F1 u3/SLICE_673
ROUTE         1     0.000      R9C27B.F1 to     R9C27B.DI1 u3/cnt_main_3[1] (to u3.clk_40khz)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_673:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to     R9C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_673:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to     R9C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.380ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_write[1]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/cnt_write[1]  (to u3.clk_40khz +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay u3/SLICE_45 to u3/SLICE_45 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path u3/SLICE_45 to u3/SLICE_45:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R15C27B.CLK to     R15C27B.Q0 u3/SLICE_45 (from u3.clk_40khz)
ROUTE        10     0.133     R15C27B.Q0 to     R15C27B.A0 u3/cnt_write[1]
CTOF_DEL    ---     0.101     R15C27B.A0 to     R15C27B.F0 u3/SLICE_45
ROUTE         1     0.000     R15C27B.F0 to    R15C27B.DI0 u3/cnt_write_s[1] (to u3.clk_40khz)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_45:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_45:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.381ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_write[5]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/cnt_write[5]  (to u3.clk_40khz +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay u3/SLICE_43 to u3/SLICE_43 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path u3/SLICE_43 to u3/SLICE_43:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R15C27D.CLK to     R15C27D.Q0 u3/SLICE_43 (from u3.clk_40khz)
ROUTE         7     0.134     R15C27D.Q0 to     R15C27D.A0 u3/cnt_write[5]
CTOF_DEL    ---     0.101     R15C27D.A0 to     R15C27D.F0 u3/SLICE_43
ROUTE         1     0.000     R15C27D.F0 to    R15C27D.DI0 u3/cnt_write_s[5] (to u3.clk_40khz)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_43:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27D.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_43:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27D.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.382ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_write[0]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/cnt_write[0]  (to u3.clk_40khz +)

   Delay:               0.369ns  (63.4% logic, 36.6% route), 2 logic levels.

 Constraint Details:

      0.369ns physical path delay u3/SLICE_46 to u3/SLICE_46 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.382ns

 Physical Path Details:

      Data path u3/SLICE_46 to u3/SLICE_46:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R15C27A.CLK to     R15C27A.Q1 u3/SLICE_46 (from u3.clk_40khz)
ROUTE         7     0.135     R15C27A.Q1 to     R15C27A.A1 u3/cnt_write[0]
CTOF_DEL    ---     0.101     R15C27A.A1 to     R15C27A.F1 u3/SLICE_46
ROUTE         1     0.000     R15C27A.F1 to    R15C27A.DI1 u3/cnt_write_s[0] (to u3.clk_40khz)
                  --------
                    0.369   (63.4% logic, 36.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_46:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27A.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_46:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to    R15C27A.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.382ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_main[0]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/cnt_main[0]  (to u3.clk_40khz +)

   Delay:               0.369ns  (63.4% logic, 36.6% route), 2 logic levels.

 Constraint Details:

      0.369ns physical path delay u3/SLICE_673 to u3/SLICE_673 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.382ns

 Physical Path Details:

      Data path u3/SLICE_673 to u3/SLICE_673:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C27B.CLK to      R9C27B.Q0 u3/SLICE_673 (from u3.clk_40khz)
ROUTE        21     0.135      R9C27B.Q0 to      R9C27B.A0 u3/cnt_main[0]
CTOF_DEL    ---     0.101      R9C27B.A0 to      R9C27B.F0 u3/SLICE_673
ROUTE         1     0.000      R9C27B.F0 to     R9C27B.DI0 u3/N_99_i (to u3.clk_40khz)
                  --------
                    0.369   (63.4% logic, 36.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_673:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to     R9C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_673:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to     R9C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.390ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_main[0]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/data[5]  (to u3.clk_40khz +)

   Delay:               0.377ns  (62.1% logic, 37.9% route), 2 logic levels.

 Constraint Details:

      0.377ns physical path delay u3/SLICE_673 to u3/SLICE_677 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.390ns

 Physical Path Details:

      Data path u3/SLICE_673 to u3/SLICE_677:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C27B.CLK to      R9C27B.Q0 u3/SLICE_673 (from u3.clk_40khz)
ROUTE        21     0.143      R9C27B.Q0 to      R7C27A.D1 u3/cnt_main[0]
CTOF_DEL    ---     0.101      R7C27A.D1 to      R7C27A.F1 u3/SLICE_677
ROUTE         1     0.000      R7C27A.F1 to     R7C27A.DI1 u3/data104_i (to u3.clk_40khz)
                  --------
                    0.377   (62.1% logic, 37.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_673:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to     R9C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_677:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to     R7C27A.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.390ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u3/cnt_main[0]  (from u3.clk_40khz +)
   Destination:    FF         Data in        u3/data[4]  (to u3.clk_40khz +)

   Delay:               0.377ns  (62.1% logic, 37.9% route), 2 logic levels.

 Constraint Details:

      0.377ns physical path delay u3/SLICE_673 to u3/SLICE_677 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.390ns

 Physical Path Details:

      Data path u3/SLICE_673 to u3/SLICE_677:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C27B.CLK to      R9C27B.Q0 u3/SLICE_673 (from u3.clk_40khz)
ROUTE        21     0.143      R9C27B.Q0 to      R7C27A.D0 u3/cnt_main[0]
CTOF_DEL    ---     0.101      R7C27A.D0 to      R7C27A.F0 u3/SLICE_677
ROUTE         1     0.000      R7C27A.F0 to     R7C27A.DI0 u3/data103_i (to u3.clk_40khz)
                  --------
                    0.377   (62.1% logic, 37.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u3/SLICE_667 to u3/SLICE_673:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to     R9C27B.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u3/SLICE_667 to u3/SLICE_677:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        20     1.220      R13C2A.Q0 to     R7C27A.CLK u3.clk_40khz
                  --------
                    1.220   (0.0% logic, 100.0% route), 0 logic levels.


================================================================================
Preference: FREQUENCY NET "u1.clk_400khz" 158.907000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.308ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/data_r[3]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/dat_h[3]  (to u1.clk_400khz +)

   Delay:               0.289ns  (46.0% logic, 54.0% route), 1 logic levels.

 Constraint Details:

      0.289ns physical path delay u1/SLICE_1254 to u1/SLICE_1204 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.308ns

 Physical Path Details:

      Data path u1/SLICE_1254 to u1/SLICE_1204:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C13D.CLK to      R5C13D.Q0 u1/SLICE_1254 (from u1.clk_400khz)
ROUTE         2     0.156      R5C13D.Q0 to      R6C13D.M1 u1/data_r[3] (to u1.clk_400khz)
                  --------
                    0.289   (46.0% logic, 54.0% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1254:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R5C13D.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_1204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R6C13D.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.309ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/data_r[6]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/dat_l[6]  (to u1.clk_400khz +)

   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.

 Constraint Details:

      0.290ns physical path delay u1/SLICE_1180 to u1/SLICE_1201 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.309ns

 Physical Path Details:

      Data path u1/SLICE_1180 to u1/SLICE_1201:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C14C.CLK to      R5C14C.Q0 u1/SLICE_1180 (from u1.clk_400khz)
ROUTE         2     0.157      R5C14C.Q0 to      R6C14C.M0 u1/data_r[6] (to u1.clk_400khz)
                  --------
                    0.290   (45.9% logic, 54.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1180:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R5C14C.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_1201:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R6C14C.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.309ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_h[2]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/ch1_dat[10]  (to u1.clk_400khz +)

   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.

 Constraint Details:

      0.290ns physical path delay u1/SLICE_1204 to u1/SLICE_1250 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.309ns

 Physical Path Details:

      Data path u1/SLICE_1204 to u1/SLICE_1250:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R6C13D.CLK to      R6C13D.Q0 u1/SLICE_1204 (from u1.clk_400khz)
ROUTE        49     0.157      R6C13D.Q0 to      R7C13D.M1 u1.dat_h[2] (to u1.clk_400khz)
                  --------
                    0.290   (45.9% logic, 54.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R6C13D.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_1250:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R7C13D.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.309ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_l[4]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/ch1_dat_fast[4]  (to u1.clk_400khz +)

   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.

 Constraint Details:

      0.290ns physical path delay u1/SLICE_1214 to u1/SLICE_1177 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.309ns

 Physical Path Details:

      Data path u1/SLICE_1214 to u1/SLICE_1177:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C14B.CLK to      R5C14B.Q0 u1/SLICE_1214 (from u1.clk_400khz)
ROUTE        53     0.157      R5C14B.Q0 to      R6C14B.M1 u1.dat_l[4] (to u1.clk_400khz)
                  --------
                    0.290   (45.9% logic, 54.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1214:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R5C14B.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_1177:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R6C14B.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.309ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/data_r[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/dat_l[1]  (to u1.clk_400khz +)

   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.

 Constraint Details:

      0.290ns physical path delay u1/SLICE_1206 to u1/SLICE_1213 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.309ns

 Physical Path Details:

      Data path u1/SLICE_1206 to u1/SLICE_1213:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C15A.CLK to      R5C15A.Q0 u1/SLICE_1206 (from u1.clk_400khz)
ROUTE         2     0.157      R5C15A.Q0 to      R5C13A.M1 u1/data_r[1] (to u1.clk_400khz)
                  --------
                    0.290   (45.9% logic, 54.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R5C15A.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_1213:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R5C13A.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.314ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/dat_h[0]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/ch1_dat[8]  (to u1.clk_400khz +)

   Delay:               0.295ns  (45.1% logic, 54.9% route), 1 logic levels.

 Constraint Details:

      0.295ns physical path delay u1/SLICE_1203 to u1/SLICE_872 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.314ns

 Physical Path Details:

      Data path u1/SLICE_1203 to u1/SLICE_872:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R6C13A.CLK to      R6C13A.Q0 u1/SLICE_1203 (from u1.clk_400khz)
ROUTE        54     0.162      R6C13A.Q0 to      R7C13A.M0 u1.dat_h[0] (to u1.clk_400khz)
                  --------
                    0.295   (45.1% logic, 54.9% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_1203:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R6C13A.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_872:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to     R7C13A.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.377ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_delay[1]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/cnt_delay[1]  (to u1.clk_400khz +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay u1/SLICE_533 to u1/SLICE_533 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path u1/SLICE_533 to u1/SLICE_533:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R3C2B.CLK to       R3C2B.Q0 u1/SLICE_533 (from u1.clk_400khz)
ROUTE         1     0.130       R3C2B.Q0 to       R3C2B.A0 u1/cnt_delay[1]
CTOF_DEL    ---     0.101       R3C2B.A0 to       R3C2B.F0 u1/SLICE_533
ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 u1/cnt_delay_s[1] (to u1.clk_400khz)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_533:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to      R3C2B.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_533:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to      R3C2B.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.377ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_delay[5]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/cnt_delay[5]  (to u1.clk_400khz +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay u1/SLICE_531 to u1/SLICE_531 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path u1/SLICE_531 to u1/SLICE_531:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R3C2D.CLK to       R3C2D.Q0 u1/SLICE_531 (from u1.clk_400khz)
ROUTE         1     0.130       R3C2D.Q0 to       R3C2D.A0 u1/cnt_delay[5]
CTOF_DEL    ---     0.101       R3C2D.A0 to       R3C2D.F0 u1/SLICE_531
ROUTE         1     0.000       R3C2D.F0 to      R3C2D.DI0 u1/cnt_delay_s[5] (to u1.clk_400khz)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_531:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to      R3C2D.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_531:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to      R3C2D.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.377ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_delay[2]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/cnt_delay[2]  (to u1.clk_400khz +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay u1/SLICE_533 to u1/SLICE_533 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path u1/SLICE_533 to u1/SLICE_533:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R3C2B.CLK to       R3C2B.Q1 u1/SLICE_533 (from u1.clk_400khz)
ROUTE         1     0.130       R3C2B.Q1 to       R3C2B.A1 u1/cnt_delay[2]
CTOF_DEL    ---     0.101       R3C2B.A1 to       R3C2B.F1 u1/SLICE_533
ROUTE         1     0.000       R3C2B.F1 to      R3C2B.DI1 u1/cnt_delay_s[2] (to u1.clk_400khz)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_533:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to      R3C2B.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_533:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to      R3C2B.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.377ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/cnt_delay[3]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u1/cnt_delay[3]  (to u1.clk_400khz +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay u1/SLICE_532 to u1/SLICE_532 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path u1/SLICE_532 to u1/SLICE_532:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R3C2C.CLK to       R3C2C.Q0 u1/SLICE_532 (from u1.clk_400khz)
ROUTE         1     0.130       R3C2C.Q0 to       R3C2C.A0 u1/cnt_delay[3]
CTOF_DEL    ---     0.101       R3C2C.A0 to       R3C2C.F0 u1/SLICE_532
ROUTE         1     0.000       R3C2C.F0 to      R3C2C.DI0 u1/cnt_delay_s[3] (to u1.clk_400khz)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path u1/SLICE_586 to u1/SLICE_532:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to      R3C2C.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path u1/SLICE_586 to u1/SLICE_532:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       258     1.098      R2C16C.Q0 to      R3C2C.CLK u1.clk_400khz
                  --------
                    1.098   (0.0% logic, 100.0% route), 0 logic levels.


================================================================================
Preference: FREQUENCY NET "dat_valid" 374.813000 MHz ;
            315 items scored, 16 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 1.677ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[13]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[13]  (to dat_valid +)

   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.

 Constraint Details:

      0.285ns physical path delay u1/SLICE_1192 to u2/SLICE_645 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.677ns

 Physical Path Details:

      Data path u1/SLICE_1192 to u2/SLICE_645:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C13C.CLK to     R10C13C.Q0 u1/SLICE_1192 (from u1.clk_400khz)
ROUTE         1     0.152     R10C13C.Q0 to     R10C13D.M1 prox_dat[13] (to dat_valid)
                  --------
                    0.285   (46.7% logic, 53.3% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1192:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to    R10C13C.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to u2/SLICE_645:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to    R10C13D.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.675ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[8]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[8]  (to dat_valid +)

   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

 Constraint Details:

      0.287ns physical path delay u1/SLICE_1308 to SLICE_643 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.675ns

 Physical Path Details:

      Data path u1/SLICE_1308 to SLICE_643:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C15A.CLK to      R8C15A.Q0 u1/SLICE_1308 (from u1.clk_400khz)
ROUTE         1     0.154      R8C15A.Q0 to      R9C15A.M0 prox_dat[8] (to dat_valid)
                  --------
                    0.287   (46.3% logic, 53.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1308:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R8C15A.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to SLICE_643:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to     R9C15A.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.569ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[6]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[6]  (to dat_valid +)

   Delay:               0.393ns  (33.8% logic, 66.2% route), 1 logic levels.

 Constraint Details:

      0.393ns physical path delay u1/SLICE_1174 to SLICE_642 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.569ns

 Physical Path Details:

      Data path u1/SLICE_1174 to SLICE_642:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C16B.CLK to      R9C16B.Q0 u1/SLICE_1174 (from u1.clk_400khz)
ROUTE         1     0.260      R9C16B.Q0 to     R10C18B.M0 prox_dat[6] (to dat_valid)
                  --------
                    0.393   (33.8% logic, 66.2% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1174:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R9C16B.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to SLICE_642:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to    R10C18B.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.563ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[3]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[3]  (to dat_valid +)

   Delay:               0.399ns  (33.3% logic, 66.7% route), 1 logic levels.

 Constraint Details:

      0.399ns physical path delay u1/SLICE_1188 to u2/SLICE_861 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.563ns

 Physical Path Details:

      Data path u1/SLICE_1188 to u2/SLICE_861:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C14C.CLK to      R9C14C.Q1 u1/SLICE_1188 (from u1.clk_400khz)
ROUTE         1     0.266      R9C14C.Q1 to      R9C16D.M1 prox_dat[3] (to dat_valid)
                  --------
                    0.399   (33.3% logic, 66.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1188:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R9C14C.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to u2/SLICE_861:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to     R9C16D.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.563ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[2]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[2]  (to dat_valid +)

   Delay:               0.399ns  (33.3% logic, 66.7% route), 1 logic levels.

 Constraint Details:

      0.399ns physical path delay u1/SLICE_1188 to u2/SLICE_861 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.563ns

 Physical Path Details:

      Data path u1/SLICE_1188 to u2/SLICE_861:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C14C.CLK to      R9C14C.Q0 u1/SLICE_1188 (from u1.clk_400khz)
ROUTE         1     0.266      R9C14C.Q0 to      R9C16D.M0 prox_dat[2] (to dat_valid)
                  --------
                    0.399   (33.3% logic, 66.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1188:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R9C14C.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to u2/SLICE_861:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to     R9C16D.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.563ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[12]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[12]  (to dat_valid +)

   Delay:               0.399ns  (33.3% logic, 66.7% route), 1 logic levels.

 Constraint Details:

      0.399ns physical path delay u1/SLICE_1253 to u2/SLICE_645 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.563ns

 Physical Path Details:

      Data path u1/SLICE_1253 to u2/SLICE_645:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13B.CLK to      R9C13B.Q1 u1/SLICE_1253 (from u1.clk_400khz)
ROUTE         1     0.266      R9C13B.Q1 to     R10C13D.M0 prox_dat[12] (to dat_valid)
                  --------
                    0.399   (33.3% logic, 66.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1253:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R9C13B.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to u2/SLICE_645:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to    R10C13D.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.563ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[0]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[0]  (to dat_valid +)

   Delay:               0.399ns  (33.3% logic, 66.7% route), 1 logic levels.

 Constraint Details:

      0.399ns physical path delay u1/SLICE_1344 to u2/SLICE_941 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.563ns

 Physical Path Details:

      Data path u1/SLICE_1344 to u2/SLICE_941:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C15D.CLK to      R9C15D.Q0 u1/SLICE_1344 (from u1.clk_400khz)
ROUTE         1     0.266      R9C15D.Q0 to      R9C16C.M0 prox_dat[0] (to dat_valid)
                  --------
                    0.399   (33.3% logic, 66.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1344:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R9C15D.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to u2/SLICE_941:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to     R9C16C.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.528ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[14]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[14]  (to dat_valid +)

   Delay:               0.434ns  (30.6% logic, 69.4% route), 1 logic levels.

 Constraint Details:

      0.434ns physical path delay u1/SLICE_1192 to u2/SLICE_646 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.528ns

 Physical Path Details:

      Data path u1/SLICE_1192 to u2/SLICE_646:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C13C.CLK to     R10C13C.Q1 u1/SLICE_1192 (from u1.clk_400khz)
ROUTE         1     0.301     R10C13C.Q1 to     R12C13B.M0 prox_dat[14] (to dat_valid)
                  --------
                    0.434   (30.6% logic, 69.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1192:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to    R10C13C.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to u2/SLICE_646:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to    R12C13B.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.480ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[11]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[11]  (to dat_valid +)

   Delay:               0.482ns  (27.6% logic, 72.4% route), 1 logic levels.

 Constraint Details:

      0.482ns physical path delay u1/SLICE_1253 to SLICE_644 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.480ns

 Physical Path Details:

      Data path u1/SLICE_1253 to SLICE_644:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13B.CLK to      R9C13B.Q0 u1/SLICE_1253 (from u1.clk_400khz)
ROUTE         1     0.349      R9C13B.Q0 to      R9C16A.M1 prox_dat[11] (to dat_valid)
                  --------
                    0.482   (27.6% logic, 72.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1253:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R9C13B.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to SLICE_644:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to     R9C16A.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.


Error: The following path exceeds requirements by 1.458ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u1/prox_dat[7]  (from u1.clk_400khz +)
   Destination:    FF         Data in        u2/prox_dat0[7]  (to dat_valid +)

   Delay:               0.504ns  (26.4% logic, 73.6% route), 1 logic levels.

 Constraint Details:

      0.504ns physical path delay u1/SLICE_1174 to SLICE_642 exceeds
      (delay constraint based on source clock period of 6.293ns and destination clock period of 2.668ns)
     -0.019ns M_HLD and
      0.000ns delay constraint less
     -1.981ns skew requirement (totaling 1.962ns) by 1.458ns

 Physical Path Details:

      Data path u1/SLICE_1174 to SLICE_642:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C16B.CLK to      R9C16B.Q1 u1/SLICE_1174 (from u1.clk_400khz)
ROUTE         1     0.371      R9C16B.Q1 to     R10C18B.M1 prox_dat[7] (to dat_valid)
                  --------
                    0.504   (26.4% logic, 73.6% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk to u1/SLICE_1174:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R9C16B.CLK u1.clk_400khz
                  --------
                    2.850   (22.3% logic, 77.7% route), 2 logic levels.

      Destination Clock Path clk to SLICE_642:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.482         C1.PAD to       C1.PADDI clk
ROUTE        59     1.116       C1.PADDI to     R2C16C.CLK clk_c
REG_DEL     ---     0.154     R2C16C.CLK to      R2C16C.Q0 u1/SLICE_586
ROUTE       258     1.098      R2C16C.Q0 to     R2C16A.CLK u1.clk_400khz
REG_DEL     ---     0.154     R2C16A.CLK to      R2C16A.Q0 u1/SLICE_1196
ROUTE        18     1.827      R2C16A.Q0 to    R10C18B.CLK dat_valid
                  --------
                    4.831   (16.4% logic, 83.6% route), 3 logic levels.

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "clk_c" 41.487000 MHz ;   |     0.000 ns|     0.379 ns|   2  
                                        |             |             |
FREQUENCY NET "u3.clk_40khz" 39.330000  |             |             |
MHz ;                                   |     0.000 ns|     0.379 ns|   2  
                                        |             |             |
FREQUENCY NET "u1.clk_400khz"           |             |             |
158.907000 MHz ;                        |     0.000 ns|     0.308 ns|   1  
                                        |             |             |
FREQUENCY NET "dat_valid" 374.813000    |             |             |
MHz ;                                   |     0.000 ns|    -1.677 ns|   1 *
                                        |             |             |
----------------------------------------------------------------------------


1 preference(marked by "*" above) not met.

No net is responsible for more than 10% of the timing errors.


Clock Domains Analysis
------------------------

Found 4 clocks:

Clock Domain: u3.clk_40khz   Source: u3/SLICE_667.Q0   Loads: 20
   Covered under: FREQUENCY NET "u3.clk_40khz" 39.330000 MHz ;

   Data transfers from:
   Clock Domain: u1.clk_400khz   Source: u1/SLICE_586.Q0
      Covered under: FREQUENCY NET "u3.clk_40khz" 39.330000 MHz ;   Transfers: 348

Clock Domain: u1.clk_400khz   Source: u1/SLICE_586.Q0   Loads: 258
   Covered under: FREQUENCY NET "u1.clk_400khz" 158.907000 MHz ;

Clock Domain: dat_valid   Source: u1/SLICE_1196.Q0   Loads: 18
   Covered under: FREQUENCY NET "dat_valid" 374.813000 MHz ;

   Data transfers from:
   Clock Domain: u1.clk_400khz   Source: u1/SLICE_586.Q0
      Covered under: FREQUENCY NET "dat_valid" 374.813000 MHz ;   Transfers: 16

Clock Domain: clk_c   Source: clk.PAD   Loads: 59
   Covered under: FREQUENCY NET "clk_c" 41.487000 MHz ;

   Data transfers from:
   Clock Domain: u1.clk_400khz   Source: u1/SLICE_586.Q0
      Covered under: FREQUENCY NET "clk_c" 41.487000 MHz ;   Transfers: 348

   Clock Domain: dat_valid   Source: u1/SLICE_1196.Q0
      Covered under: FREQUENCY NET "clk_c" 41.487000 MHz ;   Transfers: 2


Timing summary (Hold):
---------------

Timing errors: 16  Score: 23848
Cumulative negative slack: 23848

Constraints cover 2147483647 paths, 5 nets, and 8749 connections (98.29% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 12577 (setup), 16 (hold)
Score: 4294967295 (setup), 23848 (hold)
Cumulative negative slack: 23847 (4294967295+23848)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------


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